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Found 4 results

  1. Hi, this is my first try to interact with a chip, so please bear with me if my question is dumb. I'm using Basys3 with the pmod MIC3. The ADC gives back 4 leading zeros and 12 bits of data. I can get this out of pmod. But how to interpret this data? I understand the main principle of the ADC - I get a relative value between 0 and 2^12. The pmod's reference says that this value is representative of the volume and frequency. I assume that this is a kind of composite value, like X high bits are the frequency, and the rest are for volume, or similar - but couldn't find anything about such things. I was looking at all reference documentation and sample codes I could find, but maybe I was looking at wrong places. How do I get the volume and frequency separately out of the retrieved 12 bit value? Thanks
  2. I have a PmodMIC3 I would like to use with my Microblaze processor on a digilent Arty board. While trying to get the two devices to communicate through Vivado and the Vivado SDK, I have several questions that I could not find answers to. First, I assume that since there is no specific PmodMIC3 IP block, I should be using the generic PmodBridge IP block in Vivado. The 6-pin PmodMIC3 is plugged into the top row of the 2x6 Pmod output port, so the PmodBridge has it's top row interface set to SPI and the bottom row set to 'Disabled'. The PmodBridge then leads to the AXI Quad SPI block, which is one of the many things going into the Microblaze's AXI Interconnection block. (I assume that the ext_spi_clk on the Axi Quad SPI is meant to be the same ~50 MHz clock as the ext_spi_clk on the PmodOLEDrgb block, also included in this project.) Assuming that this set of connections is the 'proper' way to get PmodMIC3 to communicate with the Microblaze processor, is there any sample code I can look at, even just to see how to configure the SPI for the microphone by setting up the XSpi_Config block in Microblaze? I've been trying to reverse-engineer it from how the PmodOLEDrgb (which works fine)'s sample code uses SPI to communicate, but haven't had success yet.
  3. Hello everyone, I'm doing a little project where I use a PmodMIC and a Digilent BASYS 3 board. I understand all the code that is been given (https://github.com/bhanderson/ee324/blob/master/andrew/audioRec/PmodMicRefComp.vhd#L227), but I want to get the data to the leds on my board. My goal is to show how loud it is in a room on the leds. So for example if it's very loud all the leds shine, if it's not so loud only a few leds brighten up. But I don't know how I get the DATA on my leds, en how to see what loud or soft is, can someone help me with that? Also, if I put my PmodMIC on connector JA , what do I have to change in my entity/.XDC file? Thanks for reading and answering! Small_vhdl_projects guy
  4. I recently purchased the PmodMIC to use with my Nexys 3 board and Analog Discovery. Finally after a bit of coding, I seem to have gotten it to run continuously, but I have just a few questions. In the PmodMIC reference component PDF, it states: The VHDL component is an entity named PmodMicRefComp which has five inputs and five outputs.The input ports are a 50MHz clock,.... (BTW, I think the 5 inputs, 5 outputs thing is a typo ). But my first question is: 1) Is it possible to lower the sampling rate? Apparently the 50 MHz input clock gets divided down to 12.5 MHz inside the PmodMICRefComp. I need to record some audio data, but certainly not at 12.5 MHz! I am not sure why any audio source would ever need to be sampled that quickly, but in any case, I attempted to lower the input clock speed down a bit and my design seems to have failed. I am looking to record signals comprised mainly of human speech, so 8KHz is actually about what I need. The 2nd question is: 2) I see no mention anywhere of the format of the data output by the PmodMIC. It's 12 bits in parallel, but is that signed? unsigned? Couldn't seem to find this in the reference PDF anywhere. If this is an SPI standard convention that I'm just not aware of, sorry for asking. The 3nd question is: 3) In the state machine diagram, is there no transition directly from the "SyncData" state to the "ShiftIn" state? My code currently initiates continuous sampling by checking if nCS is HIGH and DONE is low, as indicated in the SyncData state. Then, it brings the START signal low again to return to the IDLE state, and increments a counter to keep track of the number of samples taken. On the next clock cycle, it checks if START is low, and # of samples is > 1, then pull START highagain, repeating the process. What I am wondering is: Instead of pulling START low to return to IDLE, would it not just be possible to keep START high and have nCS get pulled low again? I suppose this would need to be taken care of by the PmodMICRefComp VHDL code since that is the driver for the nCS signal after all. It would be nice if that provided VHDL component had a single bit control signal that allowed for selecting ONE TIME conversion and CONTINUOUS conversion. Thanks for taking the time to read this.