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Found 4 results

  1. Hi, this is my first try to interact with a chip, so please bear with me if my question is dumb. I'm using Basys3 with the pmod MIC3. The ADC gives back 4 leading zeros and 12 bits of data. I can get this out of pmod. But how to interpret this data? I understand the main principle of the ADC - I get a relative value between 0 and 2^12. The pmod's reference says that this value is representative of the volume and frequency. I assume that this is a kind of composite value, like X high bits are the frequency, and the rest are for volume, or similar - but couldn't find anything about suc
  2. I have a PmodMIC3 I would like to use with my Microblaze processor on a digilent Arty board. While trying to get the two devices to communicate through Vivado and the Vivado SDK, I have several questions that I could not find answers to. First, I assume that since there is no specific PmodMIC3 IP block, I should be using the generic PmodBridge IP block in Vivado. The 6-pin PmodMIC3 is plugged into the top row of the 2x6 Pmod output port, so the PmodBridge has it's top row interface set to SPI and the bottom row set to 'Disabled'. The PmodBridge then leads to the AXI Quad SPI block, which
  3. Hello everyone, I'm doing a little project where I use a PmodMIC and a Digilent BASYS 3 board. I understand all the code that is been given (https://github.com/bhanderson/ee324/blob/master/andrew/audioRec/PmodMicRefComp.vhd#L227), but I want to get the data to the leds on my board. My goal is to show how loud it is in a room on the leds. So for example if it's very loud all the leds shine, if it's not so loud only a few leds brighten up. But I don't know how I get the DATA on my leds, en how to see what loud or soft is, can someone help me with that? Also, if I put my
  4. I recently purchased the PmodMIC to use with my Nexys 3 board and Analog Discovery. Finally after a bit of coding, I seem to have gotten it to run continuously, but I have just a few questions. In the PmodMIC reference component PDF, it states: The VHDL component is an entity named PmodMicRefComp which has five inputs and five outputs.The input ports are a 50MHz clock,.... (BTW, I think the 5 inputs, 5 outputs thing is a typo ). But my first question is: 1) Is it possible to lower the sampling rate? Apparently the 50 MHz input clock gets divided down to 12.5 MHz inside the PmodMICRef