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Found 3 results

  1. Hi , Previously, I succeeded to generate a sinewave and visualize it on oscilloscope as shown in this post. Then I learnt how to use FIR filter compiler as shown in this post. Now, I am trying to visualize the FIR output on oscilloscope. I generated the bit stream file for the intended design (screenshot attached) then I viewed the output using Pmod DA3 , then the surprise it was only 1s and 0s ! as shown in the second attached picture. Note : I tried to pass 16 kHz by the FIR. I need your help about this issue. Any ideas about the reasons that make the output digital even when I am using DAC (Pmod DA3) ? Thanks.
  2. i want to generate sine wave on dac (pmodda3)( i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;
  3. Jun

    PmodDA3 (and Zybo)

    Hello, I'm new to use PmodDA3, and could get it partially worked but not fully understood. I appreciate if you could help me. (1: J3 pin, J1 jumper) When I connected J3 pin 1 and 2 to a constant voltage source with monitor, I saw +3.2V voltage appeared by before applying external voltage. I don't understand why this happens. Seen from the schematic drawing J3 pin 1 (AVdd) is connected to Vdd of AD5541A, Vlogic of AD5541A, Vin of ADR441 and V+ of AD8605. All those ports would act as input, not output. I did the first test with an internal reference, but more intereseted in using the module with the external reference. Then, for use with Vext >3.2V, should I just force to apply larger voltage difference? How about for Vext <3.2V? In either case, can I leave the J1 jumper connected? (2: Voltage clipping) My first test was to generate a saw wave from 0 to 65535 at a sampling rate of 0.868MHz (so 1 cycle = 75.5ms). Seen with a 50Ohm-terminated oscilloscope, the output lineary increased from 0V but after ~55ms it saturated at 1.9V. Because this is the very first test I might have made a mistake in VHDL coding, but could you imagine other possibility? Thanks in advance.