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Found 5 results

  1. hey everyone, I am trying to generate different waveforms of analog signals using ZEDBOARD + PMODDA2. My previous question was about Pmod+zedboard. Then, I was able to simulate the example verilog code (pmod_da2_demo) and -after changing the constraint file (.xdc)- i generated the bitstream and programmed the FPGA on my ZEDBOARD. This example piece of code generates an 12-bit digital input to the DAC and the output is expected to be a triangular waveform whose output amplitude is in between around 1.5 and 2.5 Volts. When I checked the output on the o-scope i have obtained the following wave. However, I want use both PS and PL parts of the Zedboard. That is why i need a block design which will have ZYNQ7 PS + AXI interconnect + Processor System Reset etc plus my PMODDA2's reference component i.e. DA2RefComp. DA2RefComp's inputs are CLK,RST,DATA1,DATA2 and START. If I package DA2RefComp as an IP its GUI looks like as the following: The other option is to make an RTL module using the given DA2RefComp.vhd as shown below. I tried to make the RTL module to work with Zynq7 PS. Then reading from the forum's suggestions, I tried to make the following circuit. Using AXI GPIOs and AXI Int etc are connected automatically. The triangle_0 IP module just generates triangular wave. MY question is this connection below seems correct? I couldnt make it work, yet. Secondly, the CLK input of DA2RefComp requires 50 MHz input so should I divide the clock of the PS? What should I do with the RST input of DA2RefComp? Is it just good when connected to the other resets automatically?
  2. Hey, Can I use Digilent's peripheral "Pmod DA2: Two 12-bit D/A Outputs" on zedboard ? If I check, this link, under Platforms Supported, ZedBoard is not listed. That makes me wonder if I still can use PMODDA2 and other Pmods on my zedboard? IF yes, i think we do not have an IP specificially created for PMODDA2...
  3. Dear All, I am trying to get two signals in the pmodAD1 simultaneously and send the data through the two channels in the pmodDA2 simultaneously. I got the code working for a single channel and I tried to modify it for two of them. However, even though the compilation does not give me any error, I do not see any signal out of the pmod in the oscilloscope. Please, find attached the piece of code. Any help or suggestion will be really appreciate it! Thanks a lot! 2channel main.txt 2channel pins.txt
  4. hi, I am using PMOD AD1 and PMOD DA2 on ZC702 Eval Board but it dose not work. Befor that I used my code with spart 3a, spartan6 and zedboard and my code work for all of them but when I used that code for the zc702 it dose not work. I use clock division to send 20 Mhz : This is my code: library ieee; use ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; Library UNISIM; use UNISIM.vcomponents.all; entity ad1_da2 is port( SCLK_P : in std_logic; SCLK_n : in std_logic; CS : out std_logic; -- chip select for ADC(active low) SYNC : out std_logic; -- SYNC for DAC DIN : in std_logic; -- ADC DOUT : out std_logic; -- DAC SCLK : out std_logic; -- ADC SCLK2: out std_logic -- DAC ); end ad1_da2; architecture Behavioral of ad1_da2 is component IBUFGDS is port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- FSM states type state_type is (IDLE, READ_DATA, FUNC, WRITE_DATA); -- initial state signal state : state_type := READ_DATA; -- data from the ADC signal data : std_logic_vector(11 downto 0); -- counter variable signal cnt : integer range 0 to 20 := 0; -- counter for clock division signal clkdiv : integer range 0 to 10; -- new clock from division signal newclk : std_logic := '0'; signal risingedge : std_logic := '1'; -- reset signal signal reset : std_logic := '0'; signal clk : std_logic; begin SCLK <= newclk; SCLK2 <= newclk; begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10) then -- divide 200MHz by 10 risingedge <= risingedge xor '1'; newclk <= newclk xor '1'; clkdiv <= 0; else clkdiv <= clkdiv + 1; end if; end if; end process clock_divide; main : process (CLK, reset) begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10 and risingedge = '1') then case state is when IDLE => CS <= '1'; SYNC <= '1'; if (cnt = 16) then cnt <= 0; state <= READ_DATA; else cnt <= cnt + 1; state <= IDLE; end if; when READ_DATA => CS <= '0'; SYNC <= '1'; cnt <= cnt + 1; if (cnt<4) then cnt <= cnt + 1; state <= READ_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; -- the first 4 bits are 0000 only read the last 12 data(15-cnt) <= DIN; state <= READ_DATA; elsif (cnt = 16) then cnt <= 0; state <= FUNC; end if; -- signal processing would go in this state -- but for now we don't do anything in here when FUNC => CS <= '1'; SYNC <= '1'; cnt <= 0; state <= WRITE_DATA; when WRITE_DATA => CS <= '1'; SYNC <= '0'; if (cnt = 0 or cnt = 1) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt = 2 or cnt = 3) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; DOUT <= data(15 - cnt); state <= WRITE_DATA; elsif (cnt = 16) then cnt <= 0; state <= IDLE; end if; end case; end if; end if; end process main; ibufgds_0 : IBUFGDS port map ( I => SCLK_P, IB => SCLK_n, O => CLK ); end Behavioral; Do you have an idea?
  5. Dear All, I am planning to program a PID controller on the Basys3. For this purpose, I first tried to get a signal from a function generator into the ADC (pmodAD1) and output it through the DAC (pmodDA2). This works fine. I wanna take the digital output of the ADC, multiply or divide it by a real factor and output the result through the DAC. There might be better ways of doing this but in order to specify the re number, I have created two integer numbers and apply a division between them. This would allow me to get any "real" number that I want. constant mul_number : integer := 5; constant div_number : integer := 4; signal mul_number_unsigned : unsigned(11 downto 0); signal div_number_unsigned : unsigned(11 downto 0); mul_number_unsigned <= to_unsigned(mul_number,12); div_number_unsigned <= to_unsigned(div_number,12); when mul_number_unsigned/div_number_unsigned = integer : the voltage height increases according to the set value. when mul_number_unsigned/div_number_unsigned > 1 and real : nothing happens to the signal and the same input signal is output again. when mul_number_unsigned/div_number_unsigned < 1 , positive and real : the is no output signal. I do not know how to solve the problem since the compiling does not give me any warning or error...Any help or suggestion would be really appreciated. Thanks a lot! PS: sorry for the code file format but the system did not allow me to upload a .vhd file. acd_func_dac.txt