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  1. I followed this forum and changed the constraint files of the Zybo Z720 in Vivado and successfully generate bitstream and the xsa file to import into Vitis. #Pmod Header JE set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je_pin1_io }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je_pin2_io }]; set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je_pin3_io }];
  2. Hi, this is my first try to interact with a chip, so please bear with me if my question is dumb. I'm using Basys3 with the pmod MIC3. The ADC gives back 4 leading zeros and 12 bits of data. I can get this out of pmod. But how to interpret this data? I understand the main principle of the ADC - I get a relative value between 0 and 2^12. The pmod's reference says that this value is representative of the volume and frequency. I assume that this is a kind of composite value, like X high bits are the frequency, and the rest are for volume, or similar - but couldn't find anything about suc
  3. Hello, Is there a product to connect all pins included in a female PMOD to a breadboard, so they can be accessed individually on the breadboard. thank you, Dan
  4. In Vivado (2021.2) I have created a new project for the ZedBoard that includes: MicroBlaze in microcontroller configuration with 128KiB local memory AXI interrupt controller AXI timer AXI GPIO (x2) MicroBlaze Debug Module UARTlite When I use the design assistant, the uartlite external signals (collectively, "uart_rtl)" are not connected to any IO pins and place design fails. I wrote some constraints to assign 'uart_rtl_rxd" to Pmod connection JA3 and "uart_rtl_txd" to Pmod connection JA4 (FPGA pins Y10 and AA9, respectively): set_property PACKAGE_PIN
  5. I setup 2 zybo boards, one sends data, and the other receives. The idea is to flip a switch on the sender to turn on an led on the receiving board. Th ey are configured the same, but one is coded to send, and the other to receive. Both boards are connected on two computers and can send/receive using the demo code from the digilent github. After modifying it to send the values from the switches, it does nothing. Here's what I've coded for the Send.txt and for the Receive.txt. Honestly, I'm not too sure what's going on in the code and am trying to make some sense from it. Any help would be appre
  6. I am trying to use the PmodCAN module together with PetaLinux on the ZedBoard, to display a CAN interface within the OS. So far I can make it show up in the interface overview with the following device tree overlay: /* <petalinux-project-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi */ /include/ "system-conf.dtsi" / { osc: can_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; }; &gpio0 { #interrupt-cells = <2>; interrupt-controller; }; &
  7. Hello! I am still new to all of this so bare with me. I am creating a project that involves the JSTK2 PMOD and right now I want to test the PMOD on its own with the example codes on the Diligent GitHub before integrating to my system. However, I am getting stuck at generating a bitstream. I have already done this successfully in another RTL project with the KYPD PMOD and there were no problems. I will share a screenshot of my block design. I am using the Zybo Z7-10 and I am using Vivado 2021.1. I used this link to help me get started with my IP:
  8. Kind of new to the world of FPGA tinkering. Just bought an ARTY board and the OLEDrgb pmod. Struggling to find some verilog code for the SPI driver, together with some simple demo that I could use with Vivado, perhaps a simple MicroBlaze code snipet that drives the display. I could then use this a base going forward. Does anyone recommend anything here? Thanks Steve
  9. Hello, all professionals There are 12 pins of every Pmod interface, but I discover only 10 of 12 pins are constrained to FPGA(as is described in the following screen-capture). Does that mean that the remaining two pins are not connected to FPGA?
  10. Hi, I had tried using the Pmod MTDS to build some simple projects by using the microblaze with Arty A7-35T. I had followed the "Getting Started with Digilent Pmod IPs" tutorial. The bitstream file was successfully generated and exported to the VITIS 2020.1. After I created an application project in the VITIS 2020.1, I copied the and into the src folder as requested after read the README.txt. However, when I started to build the project, it failed. It seem like missing the library files for the I had tried many methods, rebuild it, and try to export t
  11. Hello all, I'd like to connect a Pmod peripheral to the JF connector of Zybo z7-20, however, looks like the board files do not include this interface. When I open a new block design on Vivado, the "board" tab shows only JA through JE connectors. Do I have to manually map it? Maybe use the master xdc file? I'm using Vivado 2018.2 and the "new" board files from github. Thanks!
  12. Hi, I am currently working with the PmodCAN module and I am trying to make it work inside a bigger design with other AXI IPs. Unfortunately I can not find any documentation about the PmodCAN Vivado IP and the AXI address space. So I have some questions: 1. It is not clear to me, what the use case of the `AXI_LITE_GPIO` interface is. From what I can see, the PMOD interface is pre-defined to be used for the SPI communication with the MCP25625 IC; other SPI PMODS doesn't seem to need it either. I have the suspicion that some of the MCP25625 Pins can be configured as GPIOs in some way,
  13. Has anyone had troubles with the PMOD SD Flash Internface where the 10k resistors are too big for the VCU118 board. We may have to create a new PMOD as the 10k causes excessive delay in the ramp above a certain frequency.
  14. Hi Digilent staff, and fellow forum members, Just wondering if you guys had considered making a USB HID -> PS/2 PMOD board? I was thinking of something like the circuit on the Nexys 3,4 boards which uses a PIC to convert a USB keyboard to PS/2 compatible signals. Would be handy for using newer USB keyboards/mice on PMOD socket equipped FPGA boards. PS/2 devices are becoming harder to find brand new. I (for one) would be interested in a few. Kind regards, Leslie
  15. I'm using Nexys A7-100T developmennt board. I'm having issues getting Pmod I2S2 to work. This is my test design: The clocking wizard creates a 11.289MHz master clock. The tranceiver module I'm using can be found here: It seems to be generating the serial and ws (word select) clocks properly. The problem is that I'm not getting any signal from the ADC. sdout pin stays high no matter what. Even if LINE IN was floating, I would expect zeros between left and right channel data. Is the Pmod faulty or am I mis
  16. Hello Recently I have purchased Digilent PMOD AD2. I want to interface PMOD AD2 with my Xilinx Spartan-6 LX45 FPGA board. For conversion of analog signal into digital format. Could you please help me to do this. should I have to write HDL code of I2C? what is maximum speed of operation of PMOD AD2? -- Thank you Gopal Krishna
  17. pedro_uno


    Hello, I need to develop software to control an Magnetoresistive RAM (MRAM). I searched for an MRAM PMOD and found this item out of stock. The picture shows a Digilent board but I do not find it on your website. Do you have any of these on hand? Why don't they show on your site? Pete
  18. Hi, everyone here. Now, I have tried with my Pmod AD1. I used the demo code provided by the Digilent, but the value shown in the Vitis Serial Terminal is different from the value I have seen in the multimeter. For example, when I insert my sensor A into the channel A0, the value shown in 2.56. The value shown in the multimeter is 2.9V. When I insert my sensor B into the channel A1, the value shown in the Vitis Serial Terminal is 1.08. The value shown in the multimeter is about 2.1V. When the sensor induced voltage exceeds 1.8V, the AD1 value returns back to 0. I thi
  19. Greetings, It is my first time here so I apologise for my mistakes, I started a new project where I am using Nexys 3 board with a Pmod GPS module. I found a UART receiver/transmitter on the internet I wanted to test it out. So I connected the receiver to the USB UART Rx pin, in order to send from Serial COM data and then transmit back to the Serial COM the data I have sent. When I am sending a character from the serial, I receive the same character from the UART transmitter so I think that both of the components work fine. When I am sending the character A, I receive back the character A
  20. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not requi
  21. Hi, I want to connect the pmod oled display to my raspberry pi, but I'm not really getting the hang of how I should wire it. If someone can explain where to plug in each pin and how to code it that would be great. Thank you.
  22. I am currently doing the vertical farming project. And I want to put my Pmod HYGRO and Pmod AQS sensor into the same port JC. I have tried to put my Pmod HYGRO and Pmod AQS into different Pmod ports successfully. Now, I just want to combine these two sensors into one port. For example, for port JC. I want the top layer of the port connect to Pmod AQS and the bottom layer of the port to the Pmod HYGRO. So what is my first step to do when comes to vivado block design and how am I going to write my Cpp code into Vitis IDE? I did some primary research on this topic before. I may n
  23. I want to use PmodIOXP to allow both PmodAQS and PmodHYGRO to be connected into the same port in Zybo Z720. However, I do not know how to write my block design in Vivado since there is no IP for PmodIOXP in the vivado-library. Also, what kind of C++ code should I write in my Vitis after I exported my vivado file into Vitis
  24. Hello, i just bought a PmodBt2 ( ) the RN42. What i want to do is to use a Zedboard with PmodBT2 to capture all bluetooth packets that are being transmitted nearby and then analyze them using the PL and PS, so far I've managed to make the model in vivado ( thanks to some help from this forum ) but I'm unable to tell is this project is going to work from now on because I can't find a way to configure the module in this manner based on the documentation and reference manuals (
  25. I'm trying to run the PMOD BT2 core on a Zedboard, using vivado 2020.2 ( i have not tried other version to be honest ), later i'd like to use this hardware to work with petalinux and write a driver for the bluetooth module. I've been trying for a week now but i can't figure it out, i've read some related posts but i don't know what to do, please help! Here is the block design ( i have used the dilligent Digilent/vivado-