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Showing results for tags 'pmod oledrgb'.
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The reference info (online and .pdf) for the Pmod OLEDrgb falls flat (literally) when it comes to the thickness of the module. It specifies the board size is 1" x 1.4", but it doesn't say how thick the module is. And none of the photos are from a viewpoint that let me determine whether the top surface of the display is above the PMOD header connector. A side profile view (or better yet, side profile drawing) would answer these questions. Essentially, the height above bottom of circuit board at points h1 and h2 in the ascii graphic below: h1 h2 ===X===|| | __ 96 x 64 OLEDrgb__ | ===X=|| || | __ Display module __ | ------------------PMOD PCB------------------------
Hi, I am reviewing your page: https://reference.digilentinc.com/reference/pmod/pmodoledrgb/reference-manual steps 1 through 4 vs the schematic: https://reference.digilentinc.com/_media/reference/pmod/pmodoledrgb/pmodoledrgb_sch.pdf and datasheet, page 27: https://cdn-shop.adafruit.com/datasheets/SSD1331_1.2.pdf. To me, seems like there is a conflict on the power on sequence. On the reference manual page, this is the order Quick Data Acquisition Power-on Sequence where the bytes provided are in the format of (command, data) Bring Data/Command control (pin 7) logic low. Bring the Reset pin (pin 8) logic high. Bring the Vcc Enable (pin 9) logic low. Bring Pmod Enable (pin 10) to logic high and delay 20 ms to allow the 3.3V rail to become stable. Bring RES (pin 8) logic low, wait for at least 3 us, and then bring it back to logic high to reset the display controller. Wait for the reset operation to complete; this takes a maximum of 3 us to complete. But on the datasheet page, P27, this is the order. Power ON and OFF sequence The following figures illustrate the recommended power ON and power OFF sequence of SSD1331 (assume VDD and VDDIO are at the same voltage level). Power ON sequence: 1. Power ON VDD, VDDIO. 2. After VDD, VDDIO become stable, set RES# pin LOW (logic low) for at least 3us (t1) and then HIGH (logic high). 3. After set RES# pin LOW (logic low), wait for at least 3us (t2). Then Power ON VCC.(1) 4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 100ms (tAF). Vcc Enable(VCCEN) turn on Vcc first and it happens BEFORE the RES(reset) goes low in your reference manual BUT the datasheet has Vdd, Vddio coming on first which is Pmod Enable(PMODEN) and Vcc powers on AFTER reset goes low. Please Advise.