Search the Community

Showing results for tags 'pmod i2s'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 1 result

  1. Hello All, I tried the program given in http://hamsterworks.co.nz/mediawiki/index.php/Pmodi2s but there is no output on the SD. I have simulated the clock with 100MHz and got these values. clk 10ns 100Mhz Sclk 1.56Mhz mclk 40ns 25Mhz SD is always zero in-spite of setting the input data_l and data_r as Ones as shown in picture and simulation output files. I am unable to find the cause for the problem. Am i missing anything in testbench code, as I am simulating only CLK ? What changes are to be made in that code if i have to use internal SCLK. I have a PCB in which is spartan 6 FPGA is hardwired to CS4344, leaving SCLK as open/NC. I tried commenting SCLK signals and ran program but it didnt help either. Kindly help to resolve. Thanks in advance. Kotresh Kumar isim for i2s.wcfg