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Found 5 results

  1. Hi , I am using DDS IP core to visualize a 5 kHz sine wave signal. At first I simulated the IP core using Vivado simulator . I used 25 MHz clock signal. I got a sine wave signal as shown in the first attached picture. When I changed the Radix from "signed data type" to "unsigned data type" the sine wave will be like in the second attached picture. And when I implemented my design on my ARTY 7 , and connected the output of Pmod DA3 to the oscilloscope , I got a signal similar to that in the second attached picture ! As shown in the third attached picture . I changed
  2. Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect
  3. Hi @jpeyron, Kindly see the attached picture. I have the following clocking options: MIG_7series/ui_clk :83 MHz clk_wiz_0/clk_out_1 : 166 MHz And I want to feed my Pmod DA3 with the desired clocking rate. But I don't know what to choose from these clocks? So could you help me in choosing the right clock for the two pin of Pmod DA3 ? Thanks .
  4. Hi , Kindly, could you tell me what is meant by the character ~ in pin 1 and 3 ? See the attached picture. Thanks.
  5. Hi @jpeyron, @[email protected] , @Mahdi I completed my block diagram design in Vivado, and I used Microblaze IP for AXI control, and PmodDA3 IP. (1st picture) But , I want to know how to assign Constraints to the JD Connector and what are source code that should be written in SDK ? I am using Arty 7. Kindly, see the attached pictures. Looking forward your help. Thanks .