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Found 15 results

  1. Hello everyone! I wanted to challenge myself and I tried implementing an I2C master capable of configuring SSM2603. I've been so far unsuccessful, not even an ACK shows up when attempting a read. Here's the wave I'm generating (I'm trying to read reg 0x6) compared with the phases as described in the datasheet. They look the same both in Post-implementation timing simulation and when checking the probes. The ACKs from master side A(M) and ~(A(M) are given unconditionally for the time being. Question 1: do you see any issue here? Question 2: The tool infers OBUFT for ac_sda
  2. Hello, I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core. Can you helo me about these issues as soon as possible? Thank you. Best Regards.
  3. Hi. I'm using zynq board. I'm a beginner. In my design, I used aurora8b10b IP (with framing mode) . It has AXI_ tdata, tkeep ,tlast,tvalid port. I controlled these signal in my custom logic. What I want to do is reading a frame data from aurora on the PS side. When I see the axi stream fifo, I have similar ports. Can I use this? Or should we use DMA? Please tell me the proper way. thanks
  4. Dear All, "I'm working with Vivado 2018.3 and a Zybo Z7020 board" I write here because I have a very strange problem in a project that I have been developing in the past months. Namely, I've been writing a verilog code to run on a Z7020 board. This code takes user input as parameters (that are hence hard-coded) and everything works fine with this project (no errors or not understandable warnings...) Now, my job is to make sure that these so-colled parameters can be changed through a serial connection from a laptop. Hence, I've packaged my module in an IP and connected it to
  5. Dear all, I'm using Vivado 2018.3 and a Zybo Z7010 board. I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK. Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado? However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK?
  6. Hi, Problem : I am new to FPGA and I would need to understand how to read an Analog input through the XADC to analyze it on the board and then be able to accordingly output a trigger for other machines. One simple thing that I would try to do for the time being is to read in the analog signal and wire it to a led so that I could effectively see the code is working. How do I do that ? Finally, one extra constraint is that I have to limit as much as possible the use of the Zynq processor (I'm not really sure this is achievable, please excuse my lack of knowledge).
  7. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem.
  8. Well as the title says its pretty straight forward. I would like to connect a Master Port from PS to a Slave Port of the MB (PL), such that i can send data from PS to MB, but i cannot see where to enable them. Thanks for any kind of advice
  9. Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torv
  10. Hello, is there an IP that can track memory reads and writes and, eg. output them to a minicom (program thisvia XSDK)? I have tried this works fine, all tests run through. But I don't really know where to look for an approach to this. Is it possible to trigger something within the sdk when a memory access is happening ? Thanks
  11. Hello, I would like to know if the PL in Zybo boards can be used for a HDL FPGA design without the Zynq PS (no software). Is there some reference/demo/example about this case? Particularly, I want to know how to connect the USB-UART port to a custom HDL (UART) Module in the PL section, but using the same pins (i.e. MIO48, MIO49) that Zynq normally uses. Thanks in advance
  12. Hello to al, The system is built on the Zybo board in standalone mode. So far I had success sending interrupts from PL via GPIO. In order to reduce complexity I decided to try sending interrupts directly as it is shown on the included diagram. The RTL module is a simple counter sending a pulse once in a period of time. ILA confirmed the pulse. The application is supposed to count 50 interrupt events and quit. However, no triggering is happening. Clock freq is 50 MHz and a counter is 16 bit. The C-code is taken from two sources: Xilinx Timer-interrupt example and Avnet interrupt tutor
  13. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  14. Hi, Im trying to catch an interrupt from an AXI GPIO switch from my board ZCU102. I have created the following design in Vivado: The design is validated so now im using Petalinux to boot linux. I have exported the .hdf file and built petalinux but i can't boot linux.It hangs after that: Exit from FSBL NOTICE: ATF running on XCZU9EG/silicon v1/RTL5.1 at 0xfffe5000 NOTICE: BL31: Secure code at 0xfffc0000 NOTICE: BL31: Non secure code at 0x8000000 NOTICE: BL31: v1.2(release): NOTICE: BL31: Built : 17:17:47, Dec 1 2016 [ 0.000000] Booting Linu
  15. Hi, Can someone please let me know if the PmodWifi provided in this link- can be interfaced with Zedboards. I am planning to use Microblaze and build LwIP TCP raw stack on it. But I can see PmodWifi uses Microchip's MRF24WG0MA wireless chip, which according to their datasheet can be interfaced only with PIC Micro-controllers. I am a bit confused. Can someone please shed some light on me ? Thanks Goutham