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Found 12 results

  1. Dear All, "I'm working with Vivado 2018.3 and a Zybo Z7020 board" I write here because I have a very strange problem in a project that I have been developing in the past months. Namely, I've been writing a verilog code to run on a Z7020 board. This code takes user input as parameters (that are hence hard-coded) and everything works fine with this project (no errors or not understandable warnings...) Now, my job is to make sure that these so-colled parameters can be changed through a serial connection from a laptop. Hence, I've packaged my module in an IP and connected it to the PS, programmed the SDK and here is the problem : Many things work but some don't. At the beginning, I thought that the SDK used a different convention to represent signed integers (two complement, only first bit changed...) and have thereby checked that the parameters sent by the SDK where equal to hard coded values in the PL... and they are! Every single bit.. I'm now out of option to understand my problem... Has anyone had similar issues in the passt? Does anyone have a clue for me? Thank you a lot, P.S. : Please do not hesitate to write a comment if you need any further infos.
  2. Dear all, I'm using Vivado 2018.3 and a Zybo Z7010 board. I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK. Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado? However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK? The better thing would be if I could programm the FPGA through Matlab but I don't know if this is possible. Could you point me to some tutorials or the matlab functions (if they exist...). Thank you very much, NotMyCupOfTea
  3. Hi, Problem : I am new to FPGA and I would need to understand how to read an Analog input through the XADC to analyze it on the board and then be able to accordingly output a trigger for other machines. One simple thing that I would try to do for the time being is to read in the analog signal and wire it to a led so that I could effectively see the code is working. How do I do that ? Finally, one extra constraint is that I have to limit as much as possible the use of the Zynq processor (I'm not really sure this is achievable, please excuse my lack of knowledge). Product : I use the Zybo Z7 board XC7Z010-1CLG400C and Vivado Design Suite 18.3 What I have tried : I think the tutorial I've seen that best suits be needs is this one : https://cdn.instructables.com/ORIG/FRT/SYN1/IWMMH04D/FRTSYN1IWMMH04D.pdf Everything is alright until it comes to copy the instantiation template into the wrapper. I'm not really sure of how this works. After that, it is said there that the Digital input I'm interested in is named "daddr_in" ==> how should I extract it then to - let's say - connect it to a led ? Please find the Constraint file and project in the attached files and let me know if you need more. I have also made other attempts through this : http://realisenow.sdu.dk/using-the-xadc-on-the-zybo-board/ Hence a question on the fly : when I open the SDK and enter a code in C, then I'm starting to ork on the PS isn't it ? Finally, I have also tried the XADC demo project on the digilent website but couldn't sort out how to adapt it to my needs. Thank you in advance for your healp, ! Zybo-Z7-Master.xdc design_1_wrapper.v xadc_wiz_0.v
  4. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem. So the data transmission is initiated by NODE A and the control is with NODE A. NODE A will Enable the data transmission for all four UARTs. Now the problem which i am facing is, when NODE A enables the transmission for any two of the UART lines the data transmission is smooth, the problem arises only when i enable the other two. Which means the zybo is not capable of attending to those interrupts which is simultaneously coming from NODE A through four UART lines. My data contains Start byte and Stop byte, Both Start and stop byte are same character. I will attach a my Interrupt handler for reference. **************NOTE************** UART IP on PL side : UART16550 Type of UART : Interrupt driven. Software used : Vivado 2018.3 and SDK Bare metal software. UART interrupt priority : equal priority for all four UARTs. ********************************** I am not very sure about how to use four UARTs efficiently with my Zybo . Please help me with the problem, any inputs from your side will be appreciated. The following is my UART interrupt handler. *************************************************************************** static void RW1RecvHandler(void *CallBackRef, unsigned int EventData) { int i, ch, RecvCount, index; RecvCount = EventData; // repeat this loop for all chars received, i.e., for all ReceivedCount i = 0; while (i < RecvCount) { ch = RW1_RecieveBuffer[i++]; // get the received char from the buffer if(RW1_Start_byte_flag == 1) { // Stop Byte Check for RW1 if (ch == 0xc0) { // Ignore one of the two successive start byte characters if (RW1_ReceivedCount > 1) { RW1_Start_byte_flag = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; RW1_Frame_complete_flag = 1; } } else { if ((index = RW1_ReceivedCount) < TEST_BUFFER_SIZE) { RW1_Buffer[index] = ch; RW1_ReceivedCount++; } else RW1_Start_byte_flag = 0; } } // Start Byte Check for RW1 else if (ch == 0xc0) { RW1_Start_byte_flag = 1; RW1_ReceivedCount = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; // Note the cpu time when first character is received XTime_GetTime(&t_start_RW1); RW1_Frame_complete_flag = 0; } } if(RW1_Frame_complete_flag == 0) { // set up the buffer for next char in interrupt mode XUartNs550_Recv(&RW1, RW1_RecieveBuffer, 1); } } Thanks & Regards Ajeeth Kumar
  5. Well as the title says its pretty straight forward. I would like to connect a Master Port from PS to a Slave Port of the MB (PL), such that i can send data from PS to MB, but i cannot see where to enable them. Thanks for any kind of advice
  6. Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torvalds repository (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) program that I'm using shows one of two things: 1. Either the result is always an error of "SPI transfer timed out" 2. or the value in rx is the same as in tx. That is, even though the SAMA slave is demonstrably (via oscilloscope) returning something else, all the RX buffer gets is the same as was sent via the TX buffer. In fact, I can even disconnect the header that plugs the master to the slave, and this behavior becomes no different. The difference between these two results is simply a matter of removing the 1050th line in drivers/spi/spi.c when building the kernel. It's the call to wait_for_completion_timeout() in the function static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *msg). What I get from this is basically that the spi-xilinx.c driver does not know where to look for the output from the slave (MISO), and it either waits eternally for that output (if the call to wait_for_completion is left intact) OR it doesn't care to look for the data and just fills the rx buffer with the tx buffer. Now I have a very limited understanding of hardware and driver programming, so I'm basically like a blind man in the dark here. I'm adding printk() statements to spi-xilinx.c and spi.c everywhere, and checking their results with dmesg and there's just nothing enlightening (I'm using PetaLinux, and the devices all show up correctly in /dev and /sys). I'm hoping someone more experienced can shine a light on what I'm doing wrong here, or at least point me in the right direction. Attached is my device tree file, plus a screenshot of the hardware design. (the relevant node in the DT is highlighted below) amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "simple-bus"; ranges; axi_quad_spi@41e00000 { bits-per-word = <0x8>; compatible = "xlnx,xps-spi-2.00.a"; clock-names = "axi_clk", "spi_clk"; clocks = <0x1 0xf>, <0x1 0xf>; fifo-size = <0x10>; interrupt-parent = <0x4>; interrupts = <0x0 0x1d 0x1>; num-cs = <0x1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; xlnx,spi-mode = <0x0>; spidev@0 { compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x17d7840>; }; }; }; goodVersion1.dts
  7. Hello, is there an IP that can track memory reads and writes and, eg. output them to a minicom (program thisvia XSDK)? I have tried this works fine, all tests run through. But I don't really know where to look for an approach to this. Is it possible to trigger something within the sdk when a memory access is happening ? Thanks
  8. Hello, I would like to know if the PL in Zybo boards can be used for a HDL FPGA design without the Zynq PS (no software). Is there some reference/demo/example about this case? Particularly, I want to know how to connect the USB-UART port to a custom HDL (UART) Module in the PL section, but using the same pins (i.e. MIO48, MIO49) that Zynq normally uses. Thanks in advance
  9. Hello to al, The system is built on the Zybo board in standalone mode. So far I had success sending interrupts from PL via GPIO. In order to reduce complexity I decided to try sending interrupts directly as it is shown on the included diagram. The RTL module is a simple counter sending a pulse once in a period of time. ILA confirmed the pulse. The application is supposed to count 50 interrupt events and quit. However, no triggering is happening. Clock freq is 50 MHz and a counter is 16 bit. The C-code is taken from two sources: Xilinx Timer-interrupt example and Avnet interrupt tutorial controlling brightness with PWM. The issue in my opinion is that I can't find the parameter called INTERRUPT_ID. The file xparameter.h has nothing related to IRQ interrupt or anything else related to the INTERRUPT_ID or INTC_ID. Below is the last used C-code snapshot. #include <stdio.h> #include "platform.h" #include "xparameters.h" #include "xscugic.h" #include "xil_printf.h" #include "xil_exception.h" #define INTC_INTERRUPT_ID 84 // IRQ [0] #define INTC XScuGic #define INTC_HANDLER XScuGic_InterruptHandler #define INTC_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID // =0 static INTC Intc; unsigned int LED = 0; // Interrupt counter void PIsr(void *InstancePtr){ // INTERRUPT SERVICE ROUTINE(ISR) LED ++; } int SetupInterruptSystem() { int result; XScuGic *IntcInstancePtr = &Intc; XScuGic_Config *IntcConfig; IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); if (IntcConfig == NULL) { return XST_FAILURE; } result = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, IntcConfig->CpuBaseAddress); if (result != XST_SUCCESS) { return XST_FAILURE; } /* Connect the interrupt handler */ result = XScuGic_Connect(IntcInstancePtr, INTC_INTERRUPT_ID, (Xil_ExceptionHandler) PIsr, 0); if (result != XST_SUCCESS) { return result; } /* Enable the interrupt for the controller device. */ XScuGic_Enable(IntcInstancePtr, INTC_INTERRUPT_ID); Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr); Xil_ExceptionEnable(); /* Enable non-critical exceptions */ return XST_SUCCESS; } int main(void) { int status = XST_SUCCESS; xil_printf("\nLED=%d\n",LED); status = SetupInterruptSystem(); if (status != XST_SUCCESS) { return XST_FAILURE; } while (LED < 50) { } xil_printf("LED=%d",LED); return 0; } Hope someone could share insights and educate me. Thank you very much!
  10. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  11. Hi, Im trying to catch an interrupt from an AXI GPIO switch from my board ZCU102. I have created the following design in Vivado: The design is validated so now im using Petalinux to boot linux. I have exported the .hdf file and built petalinux but i can't boot linux.It hangs after that: Exit from FSBL NOTICE: ATF running on XCZU9EG/silicon v1/RTL5.1 at 0xfffe5000 NOTICE: BL31: Secure code at 0xfffc0000 NOTICE: BL31: Non secure code at 0x8000000 NOTICE: BL31: v1.2(release): NOTICE: BL31: Built : 17:17:47, Dec 1 2016 [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.4.0 (tecnobit@TBL241) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #2 SMP Thu Dec 1 17:19:05 CET 2016 [ 0.000000] Boot CPU: AArch64 Processor [410fd034] [ 0.000000] earlycon: Early serial console at MMIO 0xff000000 (options '115200n8') [ 0.000000] bootconsole [uart0] enabled [ 0.000000] cma: Reserved 128 MiB at 0x0000000078000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] PERCPU: Embedded 15 pages/cpu @ffffffc87ff71000 s23936 r8192 d29312 u61440 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: enabling workaround for ARM erratum 845719 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1034240 [ 0.000000] Kernel command line: earlycon=cdns,mmio,0xFF000000,115200n8 [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 0.000000] software IO TLB [mem 0x73fff000-0x77fff000] (64MB) mapped at [ffffffc073fff000-ffffffc077ffefff] [ 0.000000] Memory: 3908832K/4194304K available (7061K kernel code, 520K rwdata, 2692K rodata, 13604K init, 348K bss, 154400K reserved, 131072K cma-reserved) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbdffff0000 ( 247 GB) [ 0.000000] vmemmap : 0xffffffbe00000000 - 0xffffffbfc0000000 ( 7 GB maximum) [ 0.000000] 0xffffffbe00000000 - 0xffffffbe1dc00000 ( 476 MB actual) [ 0.000000] fixed : 0xffffffbffa7fd000 - 0xffffffbffac00000 ( 4108 KB) [ 0.000000] PCI I/O : 0xffffffbffae00000 - 0xffffffbffbe00000 ( 16 MB) [ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB) [ 0.000000] memory : 0xffffffc000000000 - 0xffffffc880000000 ( 34816 MB) [ 0.000000] .init : 0xffffffc000a07000 - 0xffffffc001750000 ( 13604 KB) [ 0.000000] .text : 0xffffffc000080000 - 0xffffffc000a06ff4 ( 9756 KB) [ 0.000000] .data : 0xffffffc001762000 - 0xffffffc0017e4360 ( 521 KB) [ 0.000000] Hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 64. [ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4 [ 0.000000] NR_IRQS:64 nr_irqs:64 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns [ 0.000003] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns [ 0.008316] Console: colour dummy device 80x25 [ 0.012575] console [tty0] enabled [ 0.015942] bootconsole [uart0] disabled If i boot petalinux by qemu i manage boot linux, but the interrupt i defined in the design does not appear on the system I'm beggining with embedded linux so i don't know if i'm missing something. Any idea?? pl.dtsi zynqmp.dtsi pcw.dtsi system-top.dts system-conf.dtsi
  12. Hi, Can someone please let me know if the PmodWifi provided in this link- http://store.digilentinc.com/pmodwifi-wifi-interface-802-11g/ can be interfaced with Zedboards. I am planning to use Microblaze and build LwIP TCP raw stack on it. But I can see PmodWifi uses Microchip's MRF24WG0MA wireless chip, which according to their datasheet can be interfaced only with PIC Micro-controllers. I am a bit confused. Can someone please shed some light on me ? Thanks Goutham