Search the Community

Showing results for tags 'pin'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Test and Measurement
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 6 results

  1. I am currently doing the vertical farming project. And I want to put my Pmod HYGRO and Pmod AQS sensor into the same port JC. I have tried to put my Pmod HYGRO and Pmod AQS into different Pmod ports successfully. Now, I just want to combine these two sensors into one port. For example, for port JC. I want the top layer of the port connect to Pmod AQS and the bottom layer of the port to the Pmod HYGRO. So what is my first step to do when comes to vivado block design and how am I going to write my Cpp code into Vitis IDE? I did some primary research on this topic before. I may n
  2. Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so. A single-ended clock interface in the board.xml file looks like this: <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_
  3. Here are 22+34=56 pins and I must add 4 pmods. How to declare in the IP INTEGRATOR pairs of pins as a Pmod entry?
  4. I trying to use clock capable pin U15 on the Zynq using a Zybo board. According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC): However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable. Any idea what is going on here? I'm trying to use this with a high speed camera interface. thx
  5. Hi all, I want to know the detail dimension of JTAG-USB cable connector header pin. I know this is very common header pin connector, but I want to understand its pin length and width to ensure the connection. Does anyone know about this? Thank you!
  6. I am working with the MAX32 board and want to control LD5. The schematic shows that the control for this LED is connected to RC1. However, the Reference guide (and the Excel pinout table show this as not assigned to a chipKIT pin number. If I were working with XC32 and the MPLAB X IDE, I would simply write TRISCCLR = 0x01; and then use LATCSET and LATCCLR to turn the LED on or off. What are my options if I want to stay in the Arduino IDE format? .