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Found 5 results

  1. Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so. A single-ended clock interface in the board.xml file looks like this: <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description> <port_maps> <port_map logical_port="clk" physical_port="clk" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> Which allows one to click and drag "System Clock" from the board tab into the block design and gives you a clocking wizard with a single-ended clock. I want to be able to do the exact same thing, except instead of spawning a clocking wizard with a single-ended clock, it spawns a clocking wizard with a differential clock, like this: Here is my failed attempt at creating this interface: I used "xilinx.com:signal:diff_clock_rtl:1.0" instead of "xilinx.com:signal:clock_rtl:1.0" and added another port map for the p/n signals. <interface mode="slave" name="sys_clock" type="xilinx.com:signal:diff_clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Double-Ended 100MHz oscillator used as system clock on the board that don't work none good</description> <port_maps> <port_map logical_port="CLK_P" physical_port="clk_p" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_p"/> </pin_maps> </port_map> <port_map logical_port="CLK_N" physical_port="clk_n" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_n"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> and I added the following pins to my pin file: <?xml version="1.0" encoding="UTF-8" standalone="no"?> <part_info part_name="xc7a200tffg1156-2"> <pins> <pin index="00" name ="clk_p" iostandard="LVCMOS25" loc="AG29" /> <pin index="01" name ="clk_n" iostandard="LVCMOS25" loc="AG30" /> Which gives me this message: "'System Clock' board component cannot be connected because no possible options to connect." when I try to click and drag system clock into the design: Do I need to edit the preset file, or is the syntax for my interface definition incorrect, or am I missing something else entirely? Any help is greatly appreciated. Thanks in advance
  2. Here are 22+34=56 pins and I must add 4 pmods. How to declare in the IP INTEGRATOR pairs of pins as a Pmod entry?
  3. I trying to use clock capable pin U15 on the Zynq using a Zybo board. According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC): However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable. Any idea what is going on here? I'm trying to use this with a high speed camera interface. thx
  4. Hi all, I want to know the detail dimension of JTAG-USB cable connector header pin. I know this is very common header pin connector, but I want to understand its pin length and width to ensure the connection. Does anyone know about this? Thank you!
  5. I am working with the MAX32 board and want to control LD5. The schematic shows that the control for this LED is connected to RC1. However, the Reference guide (and the Excel pinout table show this as not assigned to a chipKIT pin number. If I were working with XC32 and the MPLAB X IDE, I would simply write TRISCCLR = 0x01; and then use LATCSET and LATCCLR to turn the LED on or off. What are my options if I want to stay in the Arduino IDE format? .