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Found 5 results

  1. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io whi
  2. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that th
  3. Hi! I've implemented a Microblaze system on the ARTY board, which includes a Texas Instruments DP83848 PHY chip to manage ethernet communications. Xilkernel and example program 'echo server' works wonderfully, so any hardware issue is discarded. However, on linux (using both mainstream and xilinx' github repo), I can't get ethernetlite core to work. This is the info I can provide: axi_ethernetlite_0: [email protected] { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network";
  4. Hi, I'm trying to set up the USB OTG on Zybo board. I've done the following: 1. Checked the "Peripherals I/O pin" field for the USB0 and MIO as well for reset the PHY chip into Re-customize IP ( double click on zynq ).It matched with the schematics. 2. I have checked the devicetree auto-generated by SDK ( 2017.2 ).I have attached it. Seems to be good. 3. I have plugged my usb key on J10 ( the bigger USB connector ) as I want zybo to be a host controller. 4. The jumper JP1 is shorted. 5. The MIO 46 have to provide the reset signal to the PHY chip if I understa
  5. Hi, I'm trying to boot a linux OS ( Ubuntu core armhf ) on Zybo board. I have done the following steps: 1. Create a project in Vivado 2017.2, a project consist of a Zynq and just one custom IP core, a led controller just to turn on and of the 4 leds on board. 2. I have successfully generated the bitstream and exported the hdf in SDK. 3. In SDK I have created a project for build the fsbl successfully 4. I have built u-boot ( git clone from xilinx repo on github ) just changing the zynq_common.h file to load just the kernel and the devicetree ( not the uramdisk beca