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Found 5 results

  1. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY. A few questions come to mind: Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors... Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.
  2. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that there is a Multiplexer which is deciding the clock for either 100 or 1000 Mbps mode. The select line of this MUX is 'speedis10100_int'. I tied this signal (speedis10100_int) to an LED and found that this select line is not changing on changing the Switch (1000 to 100 Mbps). I further tried driving this select line of MUX manually by a Slide switch. Then I can observe the clock (output of MUX) changing from 125 Mhz to 25 Mhz (when i slide the switch and change the network switch to 100mbps). But still the address swap example doesn't work at 100 Mbps. Inputs of the MUX are 1) 125 Mhz generated by clock generator and, 2) mii_tx_clk (25 Mhz coming from PHY) Thanks in advance. Deepak Verma
  3. Hi! I've implemented a Microblaze system on the ARTY board, which includes a Texas Instruments DP83848 PHY chip to manage ethernet communications. Xilkernel and example program 'echo server' works wonderfully, so any hardware issue is discarded. However, on linux (using both mainstream and xilinx' github repo), I can't get ethernetlite core to work. This is the info I can provide: axi_ethernetlite_0: ethernet@40e00000 { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network"; interrupt-parent = <&microblaze_0_axi_intc>; interrupts = <1 0>; reg = <0x40e00000 0x10000>; xlnx,duplex = <0x1>; xlnx,include-global-buffers = <0x1>; xlnx,include-internal-loopback = <0x0>; xlnx,include-mdio = <0x1>; xlnx,rx-ping-pong = <0x1>; xlnx,s-axi-id-width = <0x1>; xlnx,tx-ping-pong = <0x1>; xlnx,use-internal = <0x0>; axi_ethernetlite_0_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <0>; }; }; }; phy0 section was written by me, as it was not provided by dts creation utility for the SDK. dmesg output: xilinx_emaclite 40e00000.ethernet: Device Tree Probing xilinx_emaclite 40e00000.ethernet: Failed to register mdio bus. xilinx_emaclite 40e00000.ethernet: error registering MDIO bus xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00 xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF0140000, irq=2 Relevant kernel config: CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=y CONFIG_PHYLIB=y CONFIG_DP83848_PHY=y CONFIG_XILINX_PHY=y eth0 interface appears, and ifconfig eth0 192.168.1.222 doesn't produce any error. However, no other host on the network can reach the ARTY nor viceversa, not by ping, nor by poking at any random port. Any ideas? Thanks!
  4. Hi, I'm trying to set up the USB OTG on Zybo board. I've done the following: 1. Checked the "Peripherals I/O pin" field for the USB0 and MIO as well for reset the PHY chip into Re-customize IP ( double click on zynq ).It matched with the schematics. 2. I have checked the devicetree auto-generated by SDK ( 2017.2 ).I have attached it. Seems to be good. 3. I have plugged my usb key on J10 ( the bigger USB connector ) as I want zybo to be a host controller. 4. The jumper JP1 is shorted. 5. The MIO 46 have to provide the reset signal to the PHY chip if I understand correctly 6. The connection between zynq ps and PHY is ULPI ( 12 signals from MIO 28 to 39 ) 7. When I boot the whole thing the device driver is correctly registered ( dmesg | grep usb ) but my usb key is not recognized. 8 If i stop the u-boot autoboot and issue the followings: - usb info ---> says that the usb is stopped - usb reset --> it rescan and detect correctly the host conroller and the usb key - boot --> boot the whole thing but the usb key is not recognized. I have searched a lot and, if I understand well, the following line on devicetree: usb-reset = <&gpio0 46 0>; declare that the gpio 46 have to became the reset signal for PHY chip ( active low , I have checked on Vivado into re-customize ip menu ) and in fact the "usb reset" on u-boot shell works but I don't know why I cannot recognize my usb key. I have also read that the fsbl have to issue the reset signal. I have done a search on fsbl source code and I have not found any USB reset function or something similar. The only thing that I have found is into ps7_init.c but honestly I can't understand a lot of that code... Anyone have encountered the same problem?? I have read that many peaple had problems with zybo USB OTG. I have also tried to do this into u32 FsblHookBeforeHandoff(void) but it doesn't boot ( maybe my mistake I have to retry ). Thanks in advance. Michele pcw.dtsi system-top.dts zynq-7000.dtsi
  5. Hi, I'm trying to boot a linux OS ( Ubuntu core armhf ) on Zybo board. I have done the following steps: 1. Create a project in Vivado 2017.2, a project consist of a Zynq and just one custom IP core, a led controller just to turn on and of the 4 leds on board. 2. I have successfully generated the bitstream and exported the hdf in SDK. 3. In SDK I have created a project for build the fsbl successfully 4. I have built u-boot ( git clone from xilinx repo on github ) just changing the zynq_common.h file to load just the kernel and the devicetree ( not the uramdisk because I would like to put the rootfs on sd card 2nd partition ) 5. I have built the kernel ( always from xilinx github ) using the zybo_zynq_defconfig as configuration and I have successfully generated the uImage 6. I have prepared a ubuntucorearmhf rootfs 7. I have packaged into BOOT.BIN file the fsbl, bitstream and u-boot 8. I have used the devicetree generator from xilinx github to generate my devicetree ( files attached ), with modified bootargs properly ( I hope ) 9. As you can see there is no PHY into pcw.dtsi or zynq-7000.dtsi so I have added that into a file called ethernet.dts ( made by me ) including the system-top.dts just to leave the auto-generated devicetree without modification. 10. I put the BOOT.BIN , uImage and devicetree.dtb ( compilation of ethernet.dts ) into the 1st partition of my sdcard, the rootfs into 2nd 11. At boot time the system boots without problem but it says that there is no PHY for ethernet and if I do an ifconfig the eth0 interface is absent. I have done a mistake on binding the PHY for realtek ethernet controller?? Another step I have tried is to use the BOOT.BIN and the image.ub provided by Digilent on zybo bsp 2015.4 (Digilent-Zybo-Linux-BD-v2015.4) and like this the PHY has been found and I can see the eth0 interface. I have also tried to understand the difference between my devicetree and the Petalinux one ( see .txt file ) without success. I have tried to use your zybo_base_system project instead of a clean project from scratch with same results. I have finally tried this https://github.com/MarioLizanaC/Linaro-O.S.-for-Zybo/ , a project found on github where a guy boot Linaro ( I have done it with Ubuntu core ) using as start I think your zybo_base_system but with 3.18 kernel instead of 4.9 kernel and Vivado 2015.4 instead of Vivado 2017.2 . Thanks in advance. Michele ethernet.dts pcw.dtsi system-top.dts zynq-7000.dtsi gem0_node_petalinux_bsp.txt