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Showing results for tags 'pci express'.
Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high t
Hey, In V4 version of the doc (and board?), http://digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V4.pdf (currently linked on Digilent website), the pin constraints for pcie-rx3_p, pcie-tx3_p, pcie-rx3_n and pcie-tx3_n are wrong, as they are the same as pcie rx/tx port 2 (see first half of page 19 of aforementioned pdf). In V3, https://www.digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V3.pdf (found via Google), I discovered what might be the correct values - it would be nice if someone could confirm them as being right (page 19).