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Found 15 results

  1. Hello, I am new to Xilinx and I am trying to execute the Embedded Vision Demo on Vivado 2017.4 version (attached below). This is my first time working with Block Designs and HLS so can you please guide me on how to successfully perform the mentioned demo project. Following the Read_me file I have generated the block design of the demo on Vivado. However, I am unable to export the project to SDK as it gives the error "Cannot write hardware definition file as there are no generated IPI blocks" (I am not sure if this is correct next step but I am trying follow the reference manual of z7-20
  2. Hi., Im trying to run the project available in Github for Pcam 5C camera with Zedboard using FMC Adapter. Upto bit stream is done and exported to SDK Successfully. After creating Application and adding files it is showing errors. Kindly help regarding this Version: Vivado 2018.2.1
  3. Hello, I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project. I want to replace the Digilent MIPI_D_PHY_RX with the Xilinx MIPI D-DPHY. My issue is, that the Xilinx MIPI D-PHY does not output any AXI-Stream signals and that I see permanent 'Start-of-Transmission (SoT) Error' (errsoths = '1') reported on the output port of the Xilinx MIPI D-PHY. This error occurs, according to the Xilinx MIPI D-PHY datasheet, when the HS_SETTLE parameter is not matching. The standard HS_SETTLE pa
  4. in the Zybo-Z7 P-CAM 5c Demo that is from https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.84117977.1367158795.1590938145-1282991817.1586099508 , it uses axi video stream which only contain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast in my case i want to make a video processing using vivado hls after making the IP block of my vidio processing the ip generated with ontain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvali
  5. Dear All, I am having problem communication with Pcam 5C from Genesys-2 board. There is also FMC Pcam Adapter in between. I can set I2C switch, enable A and B channels, attach logic analyzer to channel B and Pcam 5C on channel B. Pcam 5C is inserted properly - I can measurem VCC3V3 on pin 15. There is Microblaze in FPGA controlling Xilinx AXI IIC (2.0) with following code: sendData[0]= 0x31; sendData[1]= 0x00; SentByteCount = XIic_Send(IIC_BASE_ADDRESS, CAM_ID, sendData, 2, XIIC_STOP); ReceivedByteCount = XIic_Recv(IIC_BASE_ADDRESS, CAM_ID, rxBuffer, 1, XIIC_STOP); I want to
  6. Hi, I am using the Embedded Vision Demo project for Image processing. I created a new filter by creating a new IP core for it in Vivado HLS 2017.4 (for the first time) referring to the filters used in the demo and then exported it. I added the new IP in the Embedded Vision Demo in Vivado 2017.4 and made the required connections followed by generating the block design. I was able to successfully complete all these tasks, however when I try to run the demo using Xilinx SDK 2017.4 (the same way I ran the demo prior to adding new filter) it does not read the switch change in hardware for this
  7. Hello, I am working on video processing using Z7-20 Pcam 5c, for this I have created an IP block which converts rgb image to hsv. Now, I want to filter it to obtain only the yellow color. So for this I am trying to use the hls::range function to threshold the pixels in the range of yellow color. As per the manual, the template is as follows: template<int ROWS, int COLS, int SRC_T, int DST_T, typename P_T> void hls::Range ( hls::Mat<ROWS, COLS, SRC_T>& src, hls::Mat<ROWS, COLS, DST_T>& dst, P_T start, P_T end); I want to understand what does ty
  8. Dear All, what is the situation with reference design of Genesys 2 board and Pcam 5C camera? I see, that Genesys 2 board supports FMC Pcam Adapter and up to 4 cameras. So is this reference design available or user must port it by himself from another Digilent board? Genesys 2 is great board with plenty video connectors for video applications otherwise. Linas
  9. Hello, I'm working with the Zybo Pcam 5C (18.2) reference design. While using the default resolution of 1920 * 1080 - I observe the AXI Stream but exiting from the GAMA CORRECTION IP (this is last core in the video chain before the VDMA). A strange thing I noticed is that the first 4 lines at the beginning of each frame are a constant 0xAE for all pixels. ( all the red , green and blue pixels have the same value which is 0xAE ). After the first 1920 * 4 pixels non - constant data starts to arrive. Why is this ? Is this the way the sensor outputs data ?
  10. Hello, I have been trying for a while to run this PCAM 5c demo example that is provided by Digilent on a Zybo z7-20 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c The demo uses Vivado 2018.2 version, however I have been trying to execute it on the 2019.1 version. I am very new to FPGA and VHDL. I followed all the steps mentioned in the demo perfectly and did not receive any error. Although, after opening the project in the 3rd step, a pop-up window informs that the project is of the older version and I checked the option of automatically upgrading the project to current v
  11. Hello, I have been trying for a while to run this PCAM example that is provided by Digilent on a Zybo z7-10 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases After spending significant amount of time looking for solutions, I have managed to fit the design on to the board (the initial example is for a zybo z7-20) by turning off the Debug module on the MIPI CSI-2 receiver module. I have successfully exported the hardware and managed to run the provided C++ code. Even though I am able to communicate with the camera module via UART, I can not seem to acquire any
  12. Esti.A

    OpenCV and Pcam5-c

    Hi everyone, I am working in teh demo that was created by Digilent to get images from teh Pcam5-c that is connected by a MIPI CSI-2 interface to teh zybo z7-020 board. In this case, I was wondering if I decide to do the processing of the image (edge detection, enhancement of light,...) I would need to use SDx. I have seen that there are plenty of solutions in OpenCv but I dont know how the hardware proyect and the SDx project can be linked. Note, in this initial design I have teh initiallization od teh camara and platform in a C++ application file that I dont know how if I should export t
  13. vivado version :2018.2 Project source download from : https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/releases/download/v2018.2-1/ZedBoard-FMC-Pcam-Adapter-2018.2-1.zip?_ga=2.123110859.1144416419.1559024388-476519465.1556766573 In the SDK main.cc: 1.I manual add #define XPAR_MIPI_D_PHY_RX_NUM_INSTANCES 4. 2. how to define the XPAR_VIDEO_SCALER_A_DEVICE_ID ? 3.I choose random number to XPAR_VIDEO_SCALER_(A~D)_DEVICE_ID.It's show the errors, how to solve ? thank your much for your help
  14. Hello, I am using Vivado 2018.2 i downloaded "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project in original project "part" option is choosen then I created a new vivado project i choose "board" option and i created same block design with "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project. I inserted same IP blocks and made connections. I did synthesis and implementation succesfully but when i exported to SDK and i tried to boot from SD card (i used hello world template) i did not see anything on terminal but when i am trying to export original project to SDK not which i create, then i can see he
  15. nileshncsu

    PCam 5C

    How to use Pcam 5C with Raspberry PI 3+B? Thanks, Nilesh