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Found 15 results

  1. Hello, I am new to Xilinx and I am trying to execute the Embedded Vision Demo on Vivado 2017.4 version (attached below). This is my first time working with Block Designs and HLS so can you please guide me on how to successfully perform the mentioned demo project. Following the Read_me file I have generated the block design of the demo on Vivado. However, I am unable to export the project to SDK as it gives the error "Cannot write hardware definition file as there are no generated IPI blocks" (I am not sure if this is correct next step but I am trying follow the reference manual of z7-20 pcam 5c for this demo as well). Kindly guide me with the steps to be followed in order to get the demo working. Reference manual : https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.170407588.585429254.1575373921-868278974.1575373921 Thanks. EmbeddedVisionDemo.pdf
  2. Hi., Im trying to run the project available in Github for Pcam 5C camera with Zedboard using FMC Adapter. Upto bit stream is done and exported to SDK Successfully. After creating Application and adding files it is showing errors. Kindly help regarding this Version: Vivado 2018.2.1
  3. Hello, I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project. I want to replace the Digilent MIPI_D_PHY_RX with the Xilinx MIPI D-DPHY. My issue is, that the Xilinx MIPI D-PHY does not output any AXI-Stream signals and that I see permanent 'Start-of-Transmission (SoT) Error' (errsoths = '1') reported on the output port of the Xilinx MIPI D-PHY. This error occurs, according to the Xilinx MIPI D-PHY datasheet, when the HS_SETTLE parameter is not matching. The standard HS_SETTLE parameter in the Xilinx MIPI D-PHY is 145ns. The DPHY_LaneSFEN.vhd file, which is part of the Digilent MIPI D-PHY, uses a constant named 'kTHSSettle' which is set to 85ns. Even if I setup the Xilinx MIPI D-PHY to use a HS_SETTLE time of 85ns, I still see the 'Start-of-Transmission Error' reported by the Xilinx MIPI D-PHY. The camera setup is done by the Digilent pcam_vdma_hdmi application which configures the camera to run in the standard 1080p30 setup mode (2-MIPI lanes, with 420 Mbps/lane). What are the settings for the Xilinx MIPI D-PHY to decode the 2-lane MIPI signal received from the PCAM 5c camera board?
  4. in the Zybo-Z7 P-CAM 5c Demo that is from https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.84117977.1367158795.1590938145-1282991817.1586099508 , it uses axi video stream which only contain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast in my case i want to make a video processing using vivado hls after making the IP block of my vidio processing the ip generated with ontain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast axis_vidoe_tstrb axis_video_tdst axis_video_tkeep axis_video_tid after making the ip and conneting to zybo Z7 Pcam 5c demo i couldn't see the output of the camera anymore hopefully any one can help my problem to match or create an axi video stream in vivado hls for project zybo-z7 Pcam 5c demo
  5. Dear All, I am having problem communication with Pcam 5C from Genesys-2 board. There is also FMC Pcam Adapter in between. I can set I2C switch, enable A and B channels, attach logic analyzer to channel B and Pcam 5C on channel B. Pcam 5C is inserted properly - I can measurem VCC3V3 on pin 15. There is Microblaze in FPGA controlling Xilinx AXI IIC (2.0) with following code: sendData[0]= 0x31; sendData[1]= 0x00; SentByteCount = XIic_Send(IIC_BASE_ADDRESS, CAM_ID, sendData, 2, XIIC_STOP); ReceivedByteCount = XIic_Recv(IIC_BASE_ADDRESS, CAM_ID, rxBuffer, 1, XIIC_STOP); I want to read register 0x3100 of the camera on I2C address 0x78, but it fails , there is no ACK (as in attached picture). Same functions work well controlling I2C switch, so I assume there should be ACK problem. Must Pcam 5C send ACK back or it is completely ignored in Serial Camera Control Bus protocol causing I2C core failure? Thanks Linas
  6. Hi, I am using the Embedded Vision Demo project for Image processing. I created a new filter by creating a new IP core for it in Vivado HLS 2017.4 (for the first time) referring to the filters used in the demo and then exported it. I added the new IP in the Embedded Vision Demo in Vivado 2017.4 and made the required connections followed by generating the block design. I was able to successfully complete all these tasks, however when I try to run the demo using Xilinx SDK 2017.4 (the same way I ran the demo prior to adding new filter) it does not read the switch change in hardware for this new filter thus not showing any results for it. The already present filters work in the same way as before. I am new to working with Xilinx SDK and Vivado HLS, kindly guide me if I am doing anything wrong and suggest me if any changes are to be done in the SDK files. bd.pdf
  7. Hello, I am working on video processing using Z7-20 Pcam 5c, for this I have created an IP block which converts rgb image to hsv. Now, I want to filter it to obtain only the yellow color. So for this I am trying to use the hls::range function to threshold the pixels in the range of yellow color. As per the manual, the template is as follows: template<int ROWS, int COLS, int SRC_T, int DST_T, typename P_T> void hls::Range ( hls::Mat<ROWS, COLS, SRC_T>& src, hls::Mat<ROWS, COLS, DST_T>& dst, P_T start, P_T end); I want to understand what does typename P_T mean and how to define it in the header file. I am getting the following error with the current code that I have written C:/xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h: In function 'void hls::Range(hls::Mat<ROWS, COLS, SRC1_T>&, hls::Mat<ROWS, COLS, SRC2_T>&, P_T, P_T) [with int ROWS = 720, int COLS = 1280, int SRC_T = 4096, int DST_T = 4096, P_T = hls::Scalar<3, unsigned char>]': ../../../yellow_threshold.cpp:24:32: instantiated from here C:/xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h:1042:22: error: conversion from 'hls::Scalar<3, unsigned char>' to non-scalar type 'hls::_AP_T {aka ap_fixed<64, 32, (ap_q_mode)0u>}' requested make: *** [obj/yellow_threshold.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s) Please find the attached files for more details and suggest me how can I proceed. Thanks yellow_threshold.cpp yellow_threshold.h
  8. Dear All, what is the situation with reference design of Genesys 2 board and Pcam 5C camera? I see, that Genesys 2 board supports FMC Pcam Adapter and up to 4 cameras. So is this reference design available or user must port it by himself from another Digilent board? Genesys 2 is great board with plenty video connectors for video applications otherwise. Linas
  9. Hello, I'm working with the Zybo Pcam 5C (18.2) reference design. While using the default resolution of 1920 * 1080 - I observe the AXI Stream but exiting from the GAMA CORRECTION IP (this is last core in the video chain before the VDMA). A strange thing I noticed is that the first 4 lines at the beginning of each frame are a constant 0xAE for all pixels. ( all the red , green and blue pixels have the same value which is 0xAE ). After the first 1920 * 4 pixels non - constant data starts to arrive. Why is this ? Is this the way the sensor outputs data ?
  10. Hello, I have been trying for a while to run this PCAM 5c demo example that is provided by Digilent on a Zybo z7-20 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c The demo uses Vivado 2018.2 version, however I have been trying to execute it on the 2019.1 version. I am very new to FPGA and VHDL. I followed all the steps mentioned in the demo perfectly and did not receive any error. Although, after opening the project in the 3rd step, a pop-up window informs that the project is of the older version and I checked the option of automatically upgrading the project to current version. After the project opens, there is another pop-up to Report IP, I tried both the options individually i.e. Report IP and Ignore. It did not give any error in any of the following steps. But, the screen displays just a moving colour pattern and I am not able to communicate to camera module via UART as suggested in the demo. To summarise, all the steps mentioned in the demo were performed but the camera module is not working. I am unable to see the UART communication channel. I also tried following the instructions to use digilent github demo projects: https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start However, this uses the 2016.4 version. I used the SDK Handoff method and again faced the same problem. Kindly suggest possible solutions to make this demo work on 2019.1 version or tell me what have I been doing wrong. Thanks.
  11. Hello, I have been trying for a while to run this PCAM example that is provided by Digilent on a Zybo z7-10 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases After spending significant amount of time looking for solutions, I have managed to fit the design on to the board (the initial example is for a zybo z7-20) by turning off the Debug module on the MIPI CSI-2 receiver module. I have successfully exported the hardware and managed to run the provided C++ code. Even though I am able to communicate with the camera module via UART, I can not seem to acquire any video output from it. All I get is a static noise pattern, despite of trying to pick different options from the C++ menus. I am able to see the resolution change and read out the camera's registers (which seem to be correctly set according to the libraries), but that's it. What could I possibly be doing incorrectly? I see the same pattern on a different monitor and have previously tested the hdmi output from the board both through plain VHDL and the IP integrator, via the test pattern generator. I do not see any errors apart from the negative slacks in Vivado, which is a known issue..
  12. Esti.A

    OpenCV and Pcam5-c

    Hi everyone, I am working in teh demo that was created by Digilent to get images from teh Pcam5-c that is connected by a MIPI CSI-2 interface to teh zybo z7-020 board. In this case, I was wondering if I decide to do the processing of the image (edge detection, enhancement of light,...) I would need to use SDx. I have seen that there are plenty of solutions in OpenCv but I dont know how the hardware proyect and the SDx project can be linked. Note, in this initial design I have teh initiallization od teh camara and platform in a C++ application file that I dont know how if I should export to sdx file and how does this interact with the platform. Anothr queation I have is that for interacting with the openCv set-up do I must use Linux ? Kind regards Esti
  13. vivado version :2018.2 Project source download from : https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/releases/download/v2018.2-1/ZedBoard-FMC-Pcam-Adapter-2018.2-1.zip?_ga=2.123110859.1144416419.1559024388-476519465.1556766573 In the SDK main.cc: 1.I manual add #define XPAR_MIPI_D_PHY_RX_NUM_INSTANCES 4. 2. how to define the XPAR_VIDEO_SCALER_A_DEVICE_ID ? 3.I choose random number to XPAR_VIDEO_SCALER_(A~D)_DEVICE_ID.It's show the errors, how to solve ? thank your much for your help
  14. Hello, I am using Vivado 2018.2 i downloaded "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project in original project "part" option is choosen then I created a new vivado project i choose "board" option and i created same block design with "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project. I inserted same IP blocks and made connections. I did synthesis and implementation succesfully but when i exported to SDK and i tried to boot from SD card (i used hello world template) i did not see anything on terminal but when i am trying to export original project to SDK not which i create, then i can see hello world message on Terminal. Why did i not see anything in my project but i saw in original demo project? what could possibly be the problem? Hoping to read from you soon Best regards
  15. nileshncsu

    PCam 5C

    How to use Pcam 5C with Raspberry PI 3+B? Thanks, Nilesh