Search the Community
Showing results for tags 'out'.
Dear experts, I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? thanks- Shuvo
Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negati