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Found 2 results

  1. Dear experts, I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? thanks- Shuvo
  2. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo