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Found 5 results

  1. Please let me apologize, but I'm back with this issue. I downloaded the original Vivado 2015.4 OOB project, located in "Github as the Projects/user_demo directory of this repo", as gently explained by Artvb I follow the instructions, generate the project from tcl using Vivado 2015.4, and I achieved a complete Vivado 2015.4 project. Then I exported the HDF and create a local SDK15.4 project. Compiled, fine. then I downloaded to the Genesys2.... this time too the Displayport does not work (all the remaining are ok). You can imagine, I' quite disappointed. Or I'm applying every time the same mistake in the preparation of the design, or there is something else. Now, I checked possible differences between my recompiled design and what is available from GIT I recompiled an SDK 2015.4 application "G2demo" from scratch, and then i compared with downloaded files from git I noted that, while the "downloaded_system.hdf" file available in GIT sizes 1.441 Kbyte, the one regenerated by compilation spans 1535 Kbyte, That is rather strange. .lnk and .mss generated from them are exactly the same in both cases. So, I'm currently blocked, Any suggestion may be of help.
  2. Hi everybody I have a problem with the downloaded OOB design for Genesys 2: the DisplayPort seems to be properly configured, but the video does not appear. (It is not an issue related with the board, because the OOB stored on the flash of Genesys2 perform perfectly). I downloaded the design from the GIT (, dated 2017 March 18. Another ZIP is available, dated today (2017 May 2), looking inside they seems equivalent. Both designs are the previous version of the OOB, updated to Vivado 2016.4 and SDK 2016.4 So, I created the Vivado 2016 project, I asked for the proper evaluation licenses, and I achieved the bitfile. without particular problems. Then, I exported the HW to SDK, and I tried to import the sdk project/BSP (g2demo and g2demo_bsp) according to the instructions. I had a lot of errors. So, I generated a brand new BSP, with all driver updated, and I compiled the application. Everything fine. I downloaded to the board, and everything performs OK.... except DisplayPort. Console messages seems ok, the presence IRQ works, the DP is correctly trained and the screen is properly configured.... and nothing is shown. (By the way, VGA and HDMI works perfectly). Console messages are reported in screen.png I noted that the BSP delivered is really,really outdated. I tried to "patch" a .mss with the same outdated versions, but I had (as expected) a lot of bugs. Difference on versions are shown in drivers.png. Then I tried to keep the brand new BSP, and to outdate only the dp driver. It compiled, fine, but the behaviour is exactly the same. Now, I have some difficulty to proceed. It seems that the BSP you deliver is outdated, and it seems very strange. May you check your distribution, or, if correct, please give me an help about how to have correct compilation. Many thanks in advance, Marco Pavesi.
  3. Hi guys Sorry if I'm back i compiled the OOB design downloaded from your site, the ZIP file (dated 2 may 2017),,,,, the result is that Displayport continuates to be correctly trained and configured, but screen does not display. Additionally, in this version HDMI does not work too. At this point I suspect a problem in RTL (BD, constraints) sources. May you check the functionality of your distribution on a Genesys2 Board? Thanks in advance. P.S. Obviousy with other designs HDMI works fine, and with project available in flash displayport too,
  4. Dear all I prepared yesterday evening an SDK 2015.4 project, to be used with the bitfile, hdf and bmm generated by Vivado 2016.4. This way there is a discrepancy between HW and SW version, but if it works who care. Unfortunately, the elf behaves as the design recompiled under SDK 2016.4. Additionally the display link seems less stable, it continuates to disconnect and connect The connection is correct. MArco.
  5. Hi, I am running through the ARTY OOB GPIO demo, and have had no end of issues (Had to install older 2015.2 to even get the tcl to load, file locations, etc). I did get the batch file to run the FPGA load, and can see the terminal responses. Looks same as the built-in demo, except loaded from the USB. So that's all good. Want to play with SW changes, so went on to getting the design loaded.... Eventually got the demo to page 21 of the manual.... - Design is read in now OK - have block diagram, XDC, etc However, when I attempt to generate a bitstream, it complains at the synth stage: [Vivado 12-1411] Cannot set LOC property of ports, Terminal qspi_flash_sck cannot be placed on L16 (IOB_X0Y43) because the pad is already occupied by terminal qspi_flash_sck_t possibly due to user constraint ["c:/users/steve/desktop/Arty_stuff/7A35T_Arty_OOB_GPIO_demo_VIV2015_2/ipi/project_1/project_1.srcs/constrs_1/imports/xdc/design_1.xdc":9] To be clear, I haven't changed anything. This is just straight out of the demo. I did try to comment out the pin L16 constraint to see what happens. It got further.... synth and implementation completes, but it then falls over at the bitstream stage. Do I have the wrong board definition file (or version) or something? Thanks Steve