Search the Community

Showing results for tags 'nexysvideo'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 12 results

  1. Just like this post here, my out of the box example's ethernet is not working. In trying to follow the guide. Changed link speed to 100 as it said. The echo server isn't working, keeps saying the link is up then down, and my computer keeps connecting then disconnecting. All within about a second, so I don't have nearly enough time to see if anything is working even when it is "connected". So then I tried the peripheral test project, and I got an "AxiEthernet: Rx fifo over run" on the "AxiEthernetSgDmaIntrExample". So I increased the rx buffer in the IP re-customization to the max 32KB, no luck. I added some outputs to try and debug it, added the Axi dma bd ring checks to the tx & rx buffers, both pass. The example also errors with "Length mismatch" as it is not receiving everything it sent. When I do a debug launch I don't get the fifo over run, so either a coincidence or something is acting up. I also have it printing out the lengths of the rx/tx, tx is 1014, rx varies as low as 60 and as high as 216 from what I've seen so far. All the other tests (ethernet dma, timer ctr, timer interrupt, axi intc) passed. When I try unplugging the ethernet cable it hangs on waiting for the bytes to come back which I suppose makes sense. I'll attach my xsa. I've been setting the programming mode to JTAG so as far as I know the builtin example is still sitting there on the QSPI for if I need it. I couldn't get the code to build with 2020.1 even after upgrading everything, so I can't try that as a fix. EDIT: managed to get the echo working by polling the BMSR register and waiting for the negotiation complete bit to be set design_1_wrapper.xsa
  2. Hi - Looking to use the rgb2dvi_V1_2 module to get video into the FPGA. Vivado is unhappy with TMDS_Encoder.vhd Line 90, as folows: function sum_bits(u : std_logic_vector) return unsigned(3 downto 0) is Generates the following error: ERROR: 'indexed name' is not a type Any ideas on how to fix that? Many thanks, IanM
  3. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin // then count value flip over to zero, then make led on or off led <= ~led; // in the always loop, it needs to use registers end count <= count +1; // add the count value until it flips over to zero end else begin // if there is no key to be pressed, init the led to off state; led <=0; count <=1; end endmodule and I included this module in IP design. and the errors were like below. before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed' I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? Thank you for your kind answers, ...
  4. Hello everyone I am a student in bachelors and I am working on a project combining Digital Image Processing and FPGA programming. The project consists of global image thresholding but should be done real-time by the FPGA and returning the output image back to PC/laptop. I have the Nexys Video board but I still haven't figured out how to "import" the images. Is it even possible to store data in the FPGA's buffer/RAM? If someone could help me with importing/exporting data I would be very grateful. My course in FPGA includes programming in VHDL instead of Verilog, so that's the one I am using. Every information would be helpful.
  5. Hello, I bought new nexysvideo board. I read the 'important' message "press reset cpu button before turn off the board power", however I turned off the board power without pressing 'cpu reset' button by mistake. Therefore, board seems like it does not works. When I turn on the power, heat sink has no heat and OLED is turned off. Also when I toggle the switch, the LED doesn't turn on/off (remain off). Is there any solution to resolve this problem? If no, how can I repair this board? thank you.
  6. Please forgive immature English Hello I am developing a project of image processing on the NexysVideo board And it is completed and it works well at 1920 x 1080 p 60 Hz Recently I bought a new NexysVideo board And I programmed the same project but there is a problem with the operation ※ "Symptoms similar to" Defective pixel "and" Moire "appear (see attached image) I have a question Are there any specifications differences between NexysVideo board specifications this spring (2018/04) and the latest (2018/11)? Or is it exactly the same? Thank you
  7. In my project, I need to use the UART ports on the NexysVideo board to transmit signals to a Raspberry. I defined 2 signals Rx_raspi as an in std_logic and Tx_raspi as an out std_logic, and in the XDC file, they are defined as: set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports Rx_raspi ]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports Tx_raspi ]; while implementing, errors show that no ports matched. [Vivado 12-584] No ports matched 'Tx_raspi'. [Vivado 12-584] No ports matched 'Rx_raspi'. [Common 17-55] 'set_property' expects at least one object. [Common 17-55] 'set_property' expects at least one object. What was wrong?
  8. Hi all, I've got the Nexys Video and plan on creating an HDMI pass through with audio extraction. I've seen the IP provided from Digilent called dvi2rgb but i don't see any support for the audio that can be carried in the HDMI stream in this IP. First off is the Nexys Video capable of passing through the audio as well as video with the right IP? And if so is that IP Digilents? If not could someone point me to some IP (preferably created by Digilent) that can support audio? I have been trying to find some but a little help to clarify some things would be great. Thanks
  9. effisio

    Nexysvideo and Adept

    Hi I wanted to program my Nexys Video using Adept 2 Software (version 2.16.4) . However, the program could not find any specific board information, so it ends up with loading default information which only presents me the config and settings tab. The config tab tells me that adept recognizes the connected board correctly as Nexysvideo. What is going wrong here? Thanks, R.G.
  10. Jay

    Nexys Video + Camera

    Hi, I have used Atlys + VmodCam for probing camera enhancement algorithms. This time, upgrading to Nexys Video + Camera is needed due to the termination of Atlys. Is there any suggestion for what kind of camera module is the best in the market? Jay
  11. I've finally got a design for a valid DCC/EDID ROM that advertises support for HDMI input - see for more info. You can find it at and are more than welcome to include it in your designs if you want to.
  12. I'm working on a design for receving HDMI video and decided to write up my method for tuning the IDELAY and ISERDES settings to sync with the incoming stream. If you are interested, you can find it at