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Found 2 results

  1. Hello, dear collegues! I work with Nexys Video board. I use VHDL. Now I try to create project with PmodDA4. I have 4 variables which I obtained inside the project and I want to obtain it like 4 analog signals. I have found an example, but when I tried to implement it for my board it does not work (code is bellow)... If it is some example code for this PmodDA4, please send it... I could not find it for this board. -- The four left-most switches (SW15-SW12) define the command, i.e. 0011 -- The four switches after (SW11-SW8) define the address, i.e. 1111 -- The right-most switch (SW0) defines the regime: working, fast (0) or "human", slow (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity pgnd is port( btnc : in STD_LOGIC; sysclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(3 downto 0); jb : out STD_LOGIC_VECTOR(3 downto 0) ); end pgnd; architecture pgnd of pgnd is signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0, pout: STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk, btnc) begin if btnc = '1' then count <= X"0000000"; elsif rising_edge(sysclk) then count <= count + 1; end if; end process; sclkp: process(sysclk, count, btnc) begin if btnc = '1' then sclk0 <= '0'; elsif rising_edge(sysclk) then if sw(0) = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process; -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0, btnc) begin if btnc = '1' then word_count <= "101000"; -- # 40 elsif rising_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process; -- Sync signal signal_syncp: process(sclk0, word_count, btnc) begin if btnc = '1' then sync0 <= '1'; elsif rising_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process; signal_shiftp: process(sclk0, word_count, sw, count2, btnc) begin if btnc = '1' then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; elsif rising_edge(sclk0) then if word_count = "101000" then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process; -- Sawtooth data modulation data_countp: process(sclk0, word_count, btnc) begin if btnc = '1' then count2 <= X"001"; elsif rising_edge(sclk0) and word_count = "101000" then count2 <= count2 + 1; end if; end process; -- Data transmission process spip: process(sclk0, word_count, btnc) begin if btnc = '1' then pout <= '0'; elsif rising_edge(sclk0) then -- Send the signal pout <= pdata(31); end if; end process; JB(0) <= sync0; -- SYNC JB(1) <= pout; -- DOUT JB(2) <= pout; -- Just duplicate DOUT JB(3) <= sclk0; -- SCLK led(0) <= sclk0 when sw(0) = '1' else -- show the real SCLK count(24); -- or indicate device is working on higher freq led(1) <= sclk0 when sw(0) = '1' else not count(24); -- Couple the other leds only if the frequency is "human" led(2) <= pout when sw(0) = '1' else '0'; -- DOUT led(3) <= sync0 when sw(0) = '1' else '0'; -- SYNC end pgnd;
  2. Hi, I'm trying to figure out if the Nexys Video is compatible with this USB3.0 FMC board. I sent the makers an email asking if they knew if it was compatible with the Nexys Video and they replied; Our module works only with Vita57.1 or 57.4 FPGA carrier boards. Is the below mentioned Digilent board Vita57 compliant? We could not verify this based on the information posted on their website. The only details I could find myself at that it is a "Low Pin Count FMC connector" which seems like it is compatible with Vita57 in some way? Thanks for your help! Tim 'mithro' Ansell