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Found 27 results

  1. I use a Nexys 4 DDR board for some time now. I never used to have problems when programming the device. Today I tried to program the device as I did many times before, but it didn't work. It said I should check whether I connected the board properly and so on. So I checked the Jumper settings and everything. Now I tried to see whether the FTDI FT2232HQ chip is recognized. When using the bash command "lsusb" the chip is not listed anymore. Does anyone know what the problem could be? How else could I check whether the FTDI FT2232HQ chip is working or not? I need to finish a report and therefore I need the device working as soon as possible, thank you for your help.
  2. I followed the directions to a forum that show how to install board files into Vivado. Link: My issue comes when I close Vivado and reopen to create a new project, I don't see an option for selecting a nexys4 ddr board, like if I were looking for a Zybo board. I believe I copied the files over correctly. When selecting a board in Vivado, is it under a different name or would it say "nexy4 ddr"?
  3. Hi, I have started using PMOD BLE recently and I can make a connection in between BLE and PC using a terminal (with Nexys4DDR making a direct connection in between). However, when I write a VHDL code, describing what I made on the terminal one by one, the BLE device stucks at rebooting. For both applications I use the following sequence that is described in "RN4871_user_guide.pdf" page 59 : - Send $$$ - Wait a second - Send SS,40<CR> (this is to select UART Transparent feature only) - Wait a second - Send R,1<CR> - Wait a second - Wait for an ASCII entry but, at "R,1<CR> ", the BLE device turns the blue LED on (which is LD1 on schematic) and it does not shuts it off no matter what. While so, (I mean when the LED is ON) the iOS application SmartDiscover (or anyother terminal) cannot see the module. So, I cannot reach the device at all. Besides, the device returns this when connected via PC terminal (through cable) => CMD> AOK<\r><\n>CMD> Rebooting<\r><\n>%REBOOT% and returns this when FPGA communicates with the device directly => CMD> AOK<\r><\n>CMD> Rebooting<\r><\n> so, it does not return me %REBOOT% string, but seems like it stucks at some point where it is trying to reboot itself. Any help with this would be very nice at this point, Thanks in advance, Bera
  4. Hi, I've recently got a Nexys 4 DDR and I'm trying to find a keyboard that works with it. Any mouse I have works, so I'm assuming the USB connector and the PIC24 are all soldered on properly and working. I know that older and/or 'simple' keyboards are supposed to work but so far I haven't found any that actually do. I'm still looking, and I've ask around (on this forum and elsewhere) for specific make/models that are know to work. In the meantime, I've observed that when I connect the keyboard I'm using right now to type this post to the Nexys4 DDR, and run the Nexys-4-DDR-Keyboard, I keep getting 0xAA messages. If I keep a key pressed for a long time, sometimes I observe the proper scancode for the key, and then it's endless 0xAA again. According to the Nexys4 DDR reference manual: "When a keyboard or mouse is connected to the Nexys4 DDR, a “self-test passed” command (0xAA) is sent to the host." What I think is happening is that keyboard or the connection with the keyboard keeps getting reset by the PIC, which continuously sends 0xAA codes when it re-detects the keyboard. I was wondering if anyone knows what code the PIC24 is executing, if there are any patches for it, or if it's possible to see the source code to maybe fix this problem or improve compatibility. As it is, using a Nexys4 DDR is *really* hard because very little modern hardware seems to work with it. Thanks!
  5. I need a second ethernet port on my Nexys4ddr board, so I got the PMODNIC100 ethernet connector. To get started, I was trying to follow the Getting Started with Digilent Pmod IPs Tutorial, but since I do not find any IP core for PMODNIC100 in Vivado 2015.4, I do not know how to proceed. Can you please guide me regarding how to send and receive data through the PMOD NIC100 ethernet connector?
  6. Hello, I have a Nexys 4 DDR board and was looking to interface with motors for a project I am working on. I found the Pmod STEP: Stepper Motor Controller (SKU: 410-267) and had a couple of questions about it: 1) Is this Pmod compatible with my Nexys 4 DDR? 2) How many motors can this Pmod device drive. If more than one can be driven by this Pmod, can each motor be controlled individually or would the same signal be propagated to each motor attached to this Pmod. Thank you!
  7. Hi I'm planning to use the pmod ISNS20 for a project. I want to interface it with nexys4ddr board. The pmod isns20 has 2 interfaces: input : hall effect sensor's input terminals IP+ and IP-; output: ADC's output terminals: SDO; I'm familiar with the usage of the output interface with the nexys4 ddr using the SPI protocol. However, I'm not familiar with the input interface. I want to know if a sense resistor has to be used across the IP+ and IP- terminals? If so, what would be the equation of current? If no sense resistor is used, how to connect the terminals IP+ and IP- to the circuit? And again what is the equation of current being measured? I have seen the datasheets for both adc and hall effect sensor. Did not find any info on how to connect the IP+ and IP- terminals. Any help on this is highly appreciated. Thanks
  8. Hi, I am in the process of developing my own DDR2 controller as an exercise. Consequently, I'm trying to avoid using tools like MIG. Unfortunately I could not fully escape the clutches of automated tools, as in order to correctly configure the .xdc constraints file, I've had to have a peek at the following .prj file generated by the MIG in the official Digilent DDR2 Demo implementation: https://github.com/Digilent/Nexys-4-DDR-OOB/blob/master/src/ip/ddr/mig.prj I interpret the following line: "<InternalVref>1</InternalVref>" as setting the INTERNAL_VREF property to 1V. Therefore, I add the following line in my .xdc file: set_property INTERNAL_VREF 1 [get_iobanks 34] However, this configuration fails to implement for the Nexys4 DDR chip with the following error: [DRC 23-20] Rule violation (IVREF-2) INTERNAL_VREF - Bank 34 has INTERNAL_VREF set to an unsupported value (1.000V). Supported VREF values for this part are: 0.600, 0.675, 0.750, 0.900. Which value should I choose to use?
  9. Hello everybody, I'm a trainee in digital electronics, i should achieve a migration of VHDL codes from the Digilent Nexys 2 which is obsolete to another board, after some researches, I would like to work with the Nexys4DDR board. However, there is a problem of the number of connectors in the Nexys4DDR, in my project, I need at least 40 pins for my signals, it was possible with the Nexys2 thanks to the Hirose FX2 connector which disappears in the new Nexy boards. Should I choose another FPGA board or add an expansion to the Nexys4? In the last case, will there be synchronization problems?
  10. Hi! I own Nexys4DDR approx 1 year. I'm using it only for finished cores, so I'm in VHDL even not yet beginner, sadly for lack of time I began not to learn. Can anybody help me to create bitstream selector for choose which bitstream will be loaded and used? Why this Q and what I mean under help: I'm using mostly few cores, but it's for me hard to accessible Nexys4DDR board to exchange microSD card, so I want to place them into one and onlly if I find new then change/add. Help: I'm not able to create own project in VHDL, I can only follow instructions with help of possible mismatch or error. If is any public core available for this purpose can anybody recommend me one? Really it looks: do it for me and I use it. Sadly it's similar, but not for my lazy mind and hands - I have no knowledge and when I go to compile any core I always learn anything about Vivado. I'm programmer in assembler of 8-bit computers and Visual Basic with beginning C++ and also website creating, so understand HTML and others. So VHDL is not hard to recognize any action in code, but it's different to watching work of any other like to create own. Thank you for understanding and help. Miro
  11. HI, I am very new to Nexys4DDR. according to the tutorial, I try to run the board. But it's not working. 1) JP3 and JP1 connection is checked. 2) Use Prog UART port for programming 3) In Vivado, board_files were loaded Every time I run implementation without any error. But when I upload the programme, that is attached, the LD21 and LD22 is going to turn on but nothing happened according to the programme. just this thing is showing at TCL console: WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. According to the program when I turn on the sw0, the led0 should turn on. But nothing is going to turn on after turning on sw0. I tried very hard just to make a simple code with it. But I can't. If anyone can give me any suggestion. It will be highly appreciated. Thank you. top.vhd cake.vhd Nexys4_Master.xdc
  12. Hi, I'm trying to read the Configuration Flash of the Nexys4DDR. I need to achieve a relatively high speed. Here is a short summary of what I'm trying to do: My design will be controlled by an external master and there is no way to delay the masters request. The start address is latched first. After that I have about 1 us until the first read request will be applied. The subsequent reads will occur in a burst with a read cycle time of about 350 ns. Each read must deliver 16 bits of data to the master. I've been thinking about the QSPI-Flash as some kind of boot rom. And now I'm trying out if this is possible. With some combination of a high Frequency, the DDR and Quad I/O feature of the S25FL128S this could be done I believe. For the first step I got the SPI-Interface itself working using the Digilent SPI_If from the Nexys4DdrUserDemo. The SPI clock is output using the STARTUPE2. I could already read the device ID and some data successfully at 25 MHz. But at 50 MHz I'm reading garbage. Then I tested the maximum Configuration Rate (4 bit width) to find out if it is only a problem of my design. The Artix7 should be able to output a 100 MHz clock on the CCLK-Pin (FMCCK). The QSPI Flash should handle 133 MHz. But for me the maximum Configuration Rate is 40. Setting the CR to 50 will cause the FPGA to never load from SPI. Also when I attach my oscilloscope to the clock pin, the configuration at CR40 fails. So, my questions are: - What is (or should be) the maximum clock frequency of the Nexys4DDR QSPI design? - Is the FMCCK = 100 MHz only valid for configuration or is this also the maximum clock for the user design? - Do I have to constraint some attributes of the QSPI I/Os to achive a high clock? - Can this be done with "normal" logic or do I have to deal with something like SERDES? I'm using Vivado 2015.4 and have applied the contraints for "Clock signal" and "Quad SPI Flash" from the Nexys4DDR_Master.xdc from Digilent. Regards, Jago
  13. jago

    Nexys4DDR Linux

    What happened to the Embedded Linux topic on the Nexys4DDR wiki page? It was "under construction" and now it's removed. I was looking forward to see this project since I got my Nexys4DDR. What happened? Didn't the Artix7 have enough power or did Nexys4DDR have to few ressources? Regards, Jago
  14. I am using Nexys4DDR board, xc7a100t-1csg324. While using ISE 14.5 or ISE 14.7, synthesize and implementation are done without errors. But, while generating the bitstream to configure the FPGA chip, this step is stucked (i.e., Generating bitstream is running and never stop) without any error. Maybe with the same design without any modification, this step is completed normally but the many times it is not. please someone help me with this point.
  15. Here's a game of tic tac toe in VHDL for the Nexys4 DDR, written as a set of finite state machines and not as a computer running a program. The design is inspired from John F. Wakerly's tic tac toe code from his book "Digital Design: Principles and Practices", but I've completely rewritten it. The game logic is contained in the files TTTdefs.vhd, TwoInARow.vhd and game_logic.vhd. The rest of the code is there to interface with the user: to print strings to the user, to get digits and to control when moves are made. There are also two UART driver components. You should be able to set this up as a Vivado project by importing all the .vhd files and setting up the .xdc file as the constraints. When you run the bitstream, open up a 9600 bps serial connection to the Nexys4 DDR board and follow the instructions that you should see: Welcome to the computerless tic-tac-toe game. You get to make the first move. Please enter moves as digits from 1 to 9. What move would you like to make? Cheers, Warren (c) GPL3, 2015 tic_tac_toe.zip
  16. g.neri12

    Nexys 4 DDR and Adept

    I have a question about how to program the nexys 4 ddr ( .bit ) if the page said The Nexys 4 DDR is not supported by the Digilent Adept Utility then as program the .bit, I use the ISE 14.7 and adept to all projects
  17. gmv

    Nexys4 ddr resource

    Hi, are there some news about nexys4 ddr resource time to release of Embedded Linux Materials and Advanced Microblaze Design with MIG, Ethernet, UART & GPIO ?
  18. Syaoran74

    Nexys4-ddr SD card

    Hi all, I'm currently working on a project, with a component to write an incoming video stream to a sd card. I was hoping someone could point me down a direction upon to implement a solution. I've looked into the SPI interfacing method. But am unsure how to implement it. I understand that i'll have to use microblaze to act as a processor for the image processing and what not but am unsure where to process forward. I have also looked into the native sd interface, but i am to understand that to do so would require licensing? Thank you for your assistance.
  19. Finally I arrived tu run petalinux on nexys4ddr launching by jtag. Now I'm trying to generate boot file for SD/USB drive but I have some difficult because fpga can't read MCS file, just BIT by SD/USB. It's possible convert MCS to a BIT ? Any help ?
  20. ingmar

    Nexys4-ddr Board Files

    I've just downloaded the "latest?" board files for the NEXSYS4 DDR and they appear to be buggy and preventing the MIG from generating.. Vivado 2014.3.1 complains with: Any suggestions? Cheers, Ingmar, Canberra, Australia
  21. Hi, I'm hoping to PWM an extra bit(s) out of the LSB of the VGA DAC on the Neyx4ddr board so I'd like to know what kind of bandwidth the VGA DAC has. On the schematic it has a 4k resistor, but what's the capacitance ?
  22. Hi, some news about Nexys4-DDR Resource Center updates? ​I bought the board and I'm interested in sections: - Embedded Linux Materials - Advanced Microblaze Design with MIG, Ethernet, UART & GPIO - Constraint Files - Xilinx Memory Interface Generator (MIG) Project - XADC Demo
  23. Hi Digilent. It seems like the NEXYS 4 DDR Schematic is missing some pages. Specifically, the FTDI chip and UART connections. http://www.digilentinc.com/Data/Products/NEXYS4DDR/Nexys4-DDR_sch.PDF It seems like page 6 is missing. Perhaps the UART schematic is located on this page? Please advise on how to obtain the full schematic. Thank you, jliu83
  24. I recently got a Nexys 4 DDR and I'm trying to get started with a simple switch/blink-LED program. I'm using ISE Design Suite 14.5 (nt64) and I'm getting warning messages that's preventing the design from completely compiling. This is what I tried: Created a very simple design (in schematic mode) using three switch inputs, an LED output, and basic logic (AND & NAND)Added 3 ibuf, one for each input and an obuf for the outputAssigned each ibuf/obuf pin numbers from reference manual (e.g. LOC = J15)Added I/O markers, labeled A, B, C (inputs), and F (output)Get the following warning messages during compile (Implement Design > Map)WARNING:LIT:701 - PAD symbol "A" has an undefined IOSTANDARD.WARNING:LIT:702 - PAD symbol "A" is not constrained (LOC) to a specific locationThus, I'm unable to generate a Programming File (bit file?)What am I doing wrong? Am I missing a step? This was pretty much the same procedure I followed when I worked with the first-gen Basys board, using an older version of ISE (9.2), and I was able to do much more complex designs with no problems. From what I understand, I would create a design in ISE 14.5, compile it using Synthesize-XST, Implement Design, and Generate Programming File (bit file?). Then I would send the bit file to the Nexys 4 DDR using Digilent Adept? Should I start using the Vivado Design Suite? I heard it's like $2000+ for a license. I also heard there's a device-limited license?
  25. echristian

    newbie questions

    I bought a basys3 and a nexys4 ddr 1.) I tried to use web pack vivado, but when i simulate or build bitstream files(.bin or .bit) i get error no license. so i downloaded xilinx ise. 2.) with ise i can produce bit and bin files, but how do you get them to the device. I guess i could put them on a micro sd card and use the jumper.....but that does not transfer them to the non-volatile flash right? How can i transfer them to non-volatile flash? Thanks in advance Eddie