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Found 47 results

  1. NEXYS4 board cannot be detected

    Hi, I just installed vivado 2017.2 on my PC, running windows 7 Service Pack1 (64-bit). I connected my Nexys 4 board using the cable that comes with the board in the package. When I attempted to connect the board to my PC, by clicking Open Hardware Manager -> Open Target -> Auto Connect, in the Hardware window in vivado, it shows localhost(0), which means no device detected. I also get 2 warnings below: warning: cannot open library dpcomm.dll, first required symbol ftdimgr_lock, Digilent FTDI based JTAG cables cannot be supported warning: cannot open library djtg.dll, first required symbol DjtgGetPortCount, select Digilent JTAG cables cannot be supported I noticed a post in a non-English Digilent forum, in which someone else was experiencing the exact same issue. Please help. yy
  2. Nexys 4 Board Rev 4 death

    Hello digilent support team, i have got a problem with my nexys 4 board. After i connected the board to a external power supply of 5V the board is death. I connected the positive pol of the source with the positive pol of the sink and the negative pol with GND of the board. I found the schematic of the nexys 4 board and made some measurement on my death board. I measure 5V at PIN 12/13 of IC22 ADP2118 but i don't measure 3.3V at PIN 6 at IC18 ADM1086, in the schematic the name of this voltage is FT3V3. But I coundn't find the source of FT3V3 in the schematic. Can you give me the name of the IC which produces the voltage FT3V3 or the part of the schematic? I disassambled IC18 and connected PIN 15 of IC22 with VU5V0. Now the supply voltages VCC1V8, VCC3V3 and VCC1V0 are fine and LD22 is red but i don't get i connection to the board with Vivado. What's wrong with the board...?? Have a nice day... Greatings from germany
  3. I'm writing a cpu on Nexys 4 DDR, but I have a problem: The DDR2 memory on Nexys4 will be reset whenever a new .bit file is written to the FPGA. I have already generated two .bit files. One is to write instructions and data to the DDR2 memory, and the other is the cpu program. What should I do to make the DDR2 memory remain the same even after it's programmed? Thank you!
  4. Nexys 4 to PC UART communication

    Hi I am trying to send data from Nexys 4 Artix 7 FPGA Board to PC. I using uart to send the data at 9600 baud rate. The uart takes data through the switch and I am using SW(0 to 7) for this. The data transfer takes place only when button is press(btnU). I wanted to make this transfer automatic without having the need to use the button but have not been able to get it done. I have taken the code from http://www.instructables.com/id/UART-Communication-on-Basys-3-FPGA-Dev-Board-Power/?ALLSTEPS. I have made some change to replace the btnU with "State" to initiate the the data transfer. For this purpose i have written a module where the input State determines whether to initiate the uart just like the btnU. The modules transmit and transmitter are sub-modules to the XADC module. Please find my code below: module transmit ( input clk, //clock signal input State, output reg transmit //transmit signal ); always @(posedge clk) begin if (State == 1) transmit <= 1; else transmit <= 0; end endmodule ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- module transmitter( input clk, input transmit, input [7:0] data, output reg TxD ); //internal variables reg [3:0] bitcounter; reg [13:0] counter; reg state,nextstate; reg [9:0] rightshiftreg; reg shift; reg load; reg clear; //UART transmission logic always @ (posedge clk) begin counter <= counter + 1; if (counter >= 10415) begin state <= nextstate; counter <=0; if (load) rightshiftreg <= {1'b1,data,1'b0}; if (clear) bitcounter <=0; if (shift) begin rightshiftreg <= rightshiftreg >> 1; bitcounter <= bitcounter + 1; end end end //state machine always @ (posedge clk) //always @ (state or bitcounter or transmit) begin load <=0; shift <=0; clear <=0; TxD <=1; case (state) 0: begin if (transmit) begin nextstate <= 1; load <=1; shift <=0; clear <=0; end else begin nextstate <= 0; TxD <= 1; end end 1: begin // transmit state if (bitcounter >=10) begin // check if transmission is complete or not. If complete nextstate <= 0; // set nextstate back to 0 to idle state clear <=1; // set clear to 1 to clear all counters end else begin nextstate <= 1; // set nextstate to 1 to stay in transmit state TxD <= rightshiftreg[0]; // shift the bit to output TxD shift <=1; // set shift to 1 to continue shifting the data end end default: nextstate <= 0; endcase end endmodule ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The problem is that i have not been able to implement this without making use of button to initiate the data transfer. Without the use of button the communication between Nexys 4 Board and PC doesn't take place. I can only see the RX Led blinking on FPGA board but not the data on teraterm. Could you please help me to find the solution to this issue? Regards Manas
  5. Hi, I have read the possibilities of Xbee and used it using arduino Uno board. Now, I facing problem on how to interface this on Nexys 4 Artix 7 FPGA Board. Basically i'm confuse on how to proceed on FPGA board. I have already started looking on UART protocol and its implementation. Please help me out on how to proceed forward. With regards Manas
  6. NEXYS4 ARTIX -7 FPGA WITH PMOD WIFI

    Hi, I am using nexys 4 Artix 7 fpga. I want to access sensor data connected at JXADC Pmod port and the sensor output data I want to display on HTTP Server or in a web page.I already able to access GPIO pin through HTTPServer and turning on off fpga board leds.I added PmodACL2 code but it's showing error "invalid conversion from 'u32* {aka long unsigned int*}' to 'u32 {aka long unsigned int}' [-fpermissive] xspi_l.h /PmodWifiACL/src line 122 C/C++ Problem" I am facing problem in interfacing PmodACL2 with HTTPServer code for displaying sensor output at HTTPServer page or web page. Please help regarding that and if possible suggest needful resources because I have not prior experience with SDK and c++. Thanks, Dewang Shukla
  7. Nexys 4 Built-In Self-Test

    hello, I recently purchased the Nexys4 DDR and I am eager to get started, I noticed on the reference guide that it states: 17 Built-In Self-Test A demonstration configuration is loaded into the Quad-SPI flash device on the Nexys4 DDR board during manufacturing. The source code and prebuilt bitstream for this design are available for download from the Digilent website. I cannot seem to find this download page as it does not have a link (note: I underlined it to show its specified that it is available for download) can somebody please direct me to this file location please. Thank you so much in advance.
  8. hi guys ; please i want to use seven segment in nexys 4 board and i have a error i think from the constraints file i'm not understand how to use constraints file to define the seven segment this is the program and constraints file ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sev_seg is Port ( CLKIN : in std_logic; an3 : inout std_logic; an2 : inout std_logic; an1 : inout std_logic; an0 : inout std_logic; seg : out std_logic_vector(6 downto 0)); end sev_seg; architecture Behavioral of sev_seg is signal CTR : STD_LOGIC_VECTOR(12 downto 0); begin Process (CLKIN) begin if CLKIN'event and CLKIN = '1' then if (CTR="0000000000000") then if (an0='0') then an0 <= '1'; seg <= "0101011"; -- the letter n an1 <= '0'; elsif (an1='0') then an1 <= '1'; seg <= "0101011"; -- the letter n an2 <= '0'; elsif (an2='0') then an2 <= '1'; seg <= "0001000"; -- the letter A an3 <= '0'; elsif (an3='0') then an3 <= '1'; seg <= "0000110"; -- the letter E an0 <= '0'; end if; end if; CTR<=CTR+"0000000000001"; if (CTR > "1000000000000") then CTR<="0000000000000"; end if; end if; -- CLK'event and CLK = '1' End Process; end Behavioral; ------------------------------------------------------------------------------------------------------ constraints file ##7 segment display ##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA set_property PACKAGE_PIN L3 [get_ports {seg[0}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] ##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB set_property PACKAGE_PIN N1 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] ##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC set_property PACKAGE_PIN L5 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] ##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD set_property PACKAGE_PIN L4 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] ##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE set_property PACKAGE_PIN K3 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] ##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF set_property PACKAGE_PIN M2 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] ##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG set_property PACKAGE_PIN L6 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] ##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP set_property PACKAGE_PIN M4 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] ##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 set_property PACKAGE_PIN N6 [get_ports {an0}] set_property IOSTANDARD LVCMOS33 [get_ports {an0}] ##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 set_property PACKAGE_PIN M6 [get_ports {an1}] set_property IOSTANDARD LVCMOS33 [get_ports {an1}] ##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 set_property PACKAGE_PIN M3 [get_ports {an2}] set_property IOSTANDARD LVCMOS33 [get_ports {an2}] ##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 set_property PACKAGE_PIN N5 [get_ports {an3}] set_property IOSTANDARD LVCMOS ##7 segment display ##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA set_property PACKAGE_PIN L3 [get_ports {seg[0}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] ##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB set_property PACKAGE_PIN N1 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] ##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC set_property PACKAGE_PIN L5 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] ##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD set_property PACKAGE_PIN L4 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] ##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE set_property PACKAGE_PIN K3 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] ##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF set_property PACKAGE_PIN M2 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] ##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG set_property PACKAGE_PIN L6 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] ##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP set_property PACKAGE_PIN M4 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] ##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 set_property PACKAGE_PIN N6 [get_ports {an0}] set_property IOSTANDARD LVCMOS33 [get_ports {an0}] ##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 set_property PACKAGE_PIN M6 [get_ports {an1}] set_property IOSTANDARD LVCMOS33 [get_ports {an1}] ##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 set_property PACKAGE_PIN M3 [get_ports {an2}] set_property IOSTANDARD LVCMOS33 [get_ports {an2}] ##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 set_property PACKAGE_PIN N5 [get_ports {an3}] set_property IOSTANDARD LVCMOS33 [get_ports {an3}] ______________________________________________________________________________________
  9. how to connect Nexys4 with USB

    HI guys ; please i want a some help; i want to connect Nexys 4 board with RTLSDR receiver and get data from him and do processing in FPGA , some people tell me it is hard with VHDL and they propose to do this with microblaze , i need some help to do this , (advices , tutorial ....). thanks
  10. Nexys4 Ethernet Example

    hi, i tried working with this tutorial on vivado 2016.2 https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-getting-started-with-microblaze-servers/start?redirect=1 . but when i'm trying to "Generate Bitstream" , i get an error and many warnings. can't figure why, anyone can help??
  11. Missing Oscillator

    Hi, I'm working with the Nexys 4 FPGA, trying to pass the 100 MHz clock from E3 to G1 (Pin JD3), and I'm seeing no output there. When I flip the board over, I noticed X2 is populated (looks like an 8 MHz oscillator), but X1 has no component, and it's the same size and form factor. Is X1 missing something? Thanks for any help!
  12. PMOD AD1 on Nexys4

    Hi, I recently purchased a nexys 4 board and a Pmod AD1 to get short latency audio input to the fpga. Is there any vhdl example available to get audio samples from the AD1? the Digilent ressource center does not have any ... thanks, Pierre
  13. Nexys4 ethernet interface with PC

    How to send data from pc to nexys4 through ethernet, kindly guide me how to configure the ethernet protocol in nexys4. Urgent help required.
  14. ERROR INSTALL RUNTIME

    good morning I have ubuntu operating system in version 14.4, I can not install the synthesis tool Digilent Adept runtime, I get the following error with version 14.4 and 14.6 of Digilent Adept. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// root@andres-Inspiron-N5110:/home/andres/Documentos/digilent.adept.runtime_2.16.1-x86_64# sudo ./install.sh Adept Runtime Installer 64-bit operating system detected In which directory should libraries be installed? [/usr/local/lib64/digilent/adept] Installing runtime libraries..... Checking to see if libdabs.so is already installed.... No existing installation of libdabs.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdabs.so.2.16.1" Created symbolic link "/usr/local/lib64/digilent/adept/libdabs.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdabs.so.2" Checking to see if libdaci.so is already installed.... No existing installation of libdaci.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdaci.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdaci.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdaci.so.2" Checking to see if libdaio.so is already installed.... No existing installation of libdaio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdaio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdaio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdaio.so.2" Checking to see if libdemc.so is already installed.... No existing installation of libdemc.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdemc.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdemc.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdemc.so.2" Checking to see if libdepp.so is already installed.... No existing installation of libdepp.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdepp.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdepp.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdepp.so.2" Checking to see if libdftd2xx.so is already installed.... No existing installation of libdftd2xx.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdftd2xx.so.1.2.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdftd2xx.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdftd2xx.so.1" Checking to see if libdgio.so is already installed.... No existing installation of libdgio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdgio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdgio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdgio.so.2" Checking to see if libdjtg.so is already installed.... No existing installation of libdjtg.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdjtg.so.2.12.3" Created symbolic link "/usr/local/lib64/digilent/adept/libdjtg.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdjtg.so.2" Checking to see if libdmgr.so is already installed.... No existing installation of libdmgr.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdmgr.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgr.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgr.so.2" Checking to see if libdmgt.so is already installed.... No existing installation of libdmgt.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdmgt.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgt.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgt.so.2" Checking to see if libdpcomm.so is already installed.... No existing installation of libdpcomm.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpcomm.so.2.15.4" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcomm.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcomm.so.2" Checking to see if libdpcutil.so is already installed.... No existing installation of libdpcutil.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpcutil.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcutil.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcutil.so.2" Checking to see if libdpio.so is already installed.... No existing installation of libdpio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpio.so.2" Checking to see if libdpti.so is already installed.... No existing installation of libdpti.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpti.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpti.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpti.so.2" Checking to see if libdspi.so is already installed.... No existing installation of libdspi.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdspi.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdspi.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdspi.so.2" Checking to see if libdstm.so is already installed.... No existing installation of libdstm.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdstm.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdstm.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdstm.so.2" Checking to see if libdtwi.so is already installed.... No existing installation of libdtwi.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdtwi.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdtwi.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdtwi.so.2" Checking to see if libjtsc.so is already installed.... No existing installation of libjtsc.so found. Installed shared library "/usr/local/lib64/digilent/adept/libjtsc.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libjtsc.so" Created symbolic link "/usr/local/lib64/digilent/adept/libjtsc.so.2" Successfully installed runtime libraries. In which directory should system binaries be installed? [/usr/sbin] Installing system binaries..... installed "/usr/sbin/dftdrvdtch" Successfully installed system binaries in "/usr/sbin". Installing firmware images..... Successfully installed firmware images in "/usr/share/digilent/adept/data/firmware". Installing JTSC device list..... Successfully installed JTSC device list "/usr/share/digilent/adept/data/jtscdvclist.txt". Installing CoolRunner support files..... Successfully installed CoolRunner support files in "/usr/share/digilent/adept/data/xpla3". Installing CoolRunner 2 support files..... Successfully installed CoolRunner 2 support files in "/usr/share/digilent/adept/data/xbr". In which directory should the Adept Runtime Configuration file be installed? [/etc] Installing Adept Runtime configuration..... Successfully installed Adept Runtime configuration "/etc/digilent-adept.conf". Installing hotplug script..... cp: no se puede crear el fichero regular Ā«/etc/hotplug/usb/digilentusbĀ»: No existe el archivo o el directorio error: failed to install hotplug script "/etc/hotplug/usb/digilentusb" root@andres-Inspiron-N5110:/home/andres/Documentos/digilent.adept.runtime_2.16.1-x86_64# /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// help! as I solve this problem. Thank you submit
  15. I am a beginner for the nexys4 DDR board, I follow the step to build the microblaze servers as the link https://reference.digilentinc.com/nexys4-ddr:gsmbs When I run the echo_server on the sdk, I am struggling on the memory mapping problem. java.lang.RuntimeException: Failed to download ELF file Unknown Error Occured Section, 0x80000000-0x8002e173 Not Accessible from Processor I-Side Interface at com.xilinx.sdk.targetmanager.internal.TM.downloadELF(TM.java:686) at com.xilinx.sdk.debug.core.internal.AppRunner.run(AppRunner.java:129) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.runApplication(XilinxAppLaunchConfigurationDelegate.java:609) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:296) at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31) at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858) at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707) at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018) at org.eclipse.debug.internal.ui.DebugUIPlugin$7.run(DebugUIPlugin.java:1104) at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:121) I don't know what is the I-side interface of the processor. I verily linker script file for memory region mapping as suggested in the tutorial step 9. I am sure I didn't use the BRAM for mapping. So I don't think it is due the out of range memory. And I try to enlarge the stack and heap size as someone suggest could solve this problem, but still got the error message. Here is the message print out from the XMD console. Downloading Program -- C:/FPGA_project/Tutorial/microblaze_tutorial/project_server_memory/project_server_memory.sdk/echo_server/Debug/echo_server.elf section, .vectors.reset: 0x00000000-0x00000007 section, .vectors.sw_exception: 0x00000008-0x0000000f section, .vectors.interrupt: 0x00000010-0x00000017 section, .vectors.hw_exception: 0x00000020-0x00000027 section, .text: 0x80000000-0x8002e177 section, .init: 0x8002e178-0x8002e1b3 section, .fini: 0x8002e1b4-0x8002e1d3 It seems the problem is mapping the .text into that range of memory. attached is the lscript.ld MEMORY { microblaze_0_local_memory_ilmb_bram_if_cntlr_microblaze_0_local_memory_dlmb_bram_if_cntlr : ORIGIN = 0x50, LENGTH = 0x1FB0 mig_7series_0 : ORIGIN = 0x80000000, LENGTH = 0xA000000 } So can anyone explain why we got this problem? and how to solve this efficiently? It seems that everyone got the same error message but have different solution get out. lscript.ld
  16. Hi! I'm here really new and I'm only beginning learn VHDL. I'm owner of Nexys4DDR and using it for first for Mega 65 and Apple II computer cores, now I want to use for own programming. First Q is maybe stupid, but very useful. I'm loading cores from microSD card and if I want to use one I must to select first card, when second, select second card... always push and pull any. I want to have all on one microSD card. How to create any core bitstream selector? If any, which programming language to use? Thank you for at least reading this. Miro
  17. Reprogram (reset) FPGA

    Hello all, I have a Nexys4 DDR and I want to reprogram it, as it's done with "PROG" button. As example I want to connect the IPROG/Program_B signal to be triggered when something happens like the output of my circuit is "1", or using a switch. How can I do that? I've read documentation about multiboot but I don't want to load two bitstreams, only one and reprogram the FPGA with it when I want. I suppose that using the Program_b signal is the way to go but I don't know how I can use it. Some code, tutorial or documentation would be appreciated. Thank you
  18. Nexys4 Altium sources

    Hi, I would like to get the Altium schematics sources for the Nexys4 Artix7 board. Thanks!
  19. Nexys 4 DDR sram-to-ddr map problem

    Hello, I am using Xilinx ISE 14.7 I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end. I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons. I started Translate and Map, Translate returned a lot of messages like: And Map returned: I found there http://www.xilinx.com/support/answers/34900.html a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the same). It removed these errors but now Map returned different error: I am using the ngc file from the /Netlist directory but i also tried to use files from /Source and i had the same problem. The solution for this issue on Xilinx Support tells me that i need to correct pin-out but I have downloaded official component so i think that it should work without any modifications. Could someone help me with this issue?
  20. Nexys4 VGA Tic Tac Toe

    Purely player vs player Tic Tac Toe, using one fpga. The game state is viewed through the VGA port, displaying the X's and O's in the grid on a connected monitor. User control is through the five push buttons, left/right/up/down control selection of a square, center confirms the selection. The project figures out when the game has ended and lights an RGB LED, and colors the winning line/s green. https://github.com/verdoss/TicTacToe Originally created for the WSU Hackathon in February 2015, so I apologize if the source is a little convoluted, with the exception of most of the comments, the project was written in 24 hours.
  21. Hi Everyone, I'm new to almost every kind of programming, be it VHDL, C++ or digital electronics in general, but still I convinced myself to buy a nexys4-DDR board with two A/D and D/A converter Pmods to implement a feedback loop to a system. For my project I designed a VHDL project, which takes in data through A/D and does some DSP and returns the result via D/A converter. Now, to make the project very user friendly and tuneable in order to get the desired results after tuning, I designed a GUI App in C++ which employs the dpcutil.dll API for data transfer Functions. My App works as I can see the device table and can select my board, when called. Now the problem is that, it seems the data transfer functions of the API, only works if I've a VHDL module like dpimref.vd for data transaction, which employs EPP scheme(till now everything is fine, as i can implement the dpimref.vd module), but the input to this module are of EPP scheme(pdb[7:0], astb, pwr, dstb etc.), whereas the Nexys-4 board uses USB-UART or JTAG for programming(TXD_IN, RXD_OUT, CTS, RTS) as can be seen in the constraint file. So, do I have to write a SIPO module(component), which converts the serial data to parallel inout, and follows the rules of transaction between API and dpimref ? If so, can anybody please show me some example or tutorial or any reference where it has been done! Thanks a lot.
  22. Nexys4 BSP for EDK needed!!

    What about Nexys4 BSP for EDK XPS wizard? I am using Xilinx 14.7 for Embedded Systems with tihis card and i cant find these suppor t files to use in wizard like other boards. Thanks in advance
  23. Using Cellular RAM on Nexys 4

    Hello! I am using Xilinx Vivado 2015.3 and Digilent Nexys 4 board. There is Cellular RAM on the board which has SRAM interface. What kind of IP do I need to make it work on MicroBlaze-based design? Example simple design would be greatly appreciated. Thanks, Alexander.
  24. Nexys 4 PMOD spacing

    Hello, I'm designing an adapter PCB to interface with the three PMOD connectors on the right hand side of the Nexys 4 (JADC, JC, JD). I can only find a schematic but in order to have the correct spacing between the connectors I would need a board file or a CAD file or the like. The reference manual doesn't have any measurements either. Has anybody got the measurements or a file where I could read them? Thanks in advance!
  25. Instantiating Nexys4 SRAM to DDR Component

    I'm about to play with the Nexys4 DDR "SRAM to DDR" component, but I've never used a MIG or a pre-existing netlist before. The instructions say "Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project." Can someone help me with an explanation on how to do this?! I'm using Vivado 2015.1. Thanks all! Warren