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Found 15 results

  1. When I ported the w11 CPU design from Nexys4 to Nexys A7 I didn't use the SRAM to DDR component but wrote my own interface layer which queues writes and includes a 'last row buffer', see sramif_mig_nexys4d and sramif2migui_core. I had a look at the Nexys 4 DDR Xilinx MIG Project and was a bit astonished to see that the SYS_CLK was 200 MHz <TimePeriod>3333</TimePeriod> <PHYRatio>2:1</PHYRatio> <InputClkFreq>200.02</InputClkFreq> I really wonder why Digilent recommends this. It is possible to use 100 MHz, to use the board cl
  2. I tend to create a project for DDR interface, as I searched I found, the straightforward way is to use the Digilent-provided DDR-to-SRAM adapter module which instantiates the memory controller and uses an asynchronous SRAM bus for interfacing with user logic. I follow this link, https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start and now I need to know about the Protocol. would anyone please let me know the used protocol in the mentioned programme.
  3. Hi, I recently discovered that the wrong scan codes are sent for certain keys. This is tested with my own PS2 keyboard controller, and the same behaviour is present with the official demo: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-keyboard-demo/start I have tested two keyboards: One Logitech K120, and one Microsoft comfort curve 3000. The following behaviour is exhibited: Left arrow set 2 scancode should be: E0 6B / E0 F0 6B. Actual: 6B / F0 6B Up arrow set 2 scancode should be: E0 75 / E0 F0 75. Actual: 75 / F0 75 Down arrow set
  4. Hello. I wish to write assembly code for ADXL362 accelerometer on Nexys4 DDR and compile for use with Picoblaze softcore processor. Are there any assembly routines that I can use to establish communication with the accelerometer please? Any links to code would be appreciated.
  5. fLx

    Nexys4 ddr Ethernet

    Please need help on knowing the function in which nexys4 ddr ethernet echo_server example use to send back data sent to it from the client "tera term".......?
  6. ched

    nexys4 ddr ram pin

    Hi, I am trying to find the pin of the ram of the nexys4 ddr to update my constraints, but I can't find it in the provided xdc file. Please help
  7. Hello I want to send an image from nexys4 DDR to basys3 through pmod. Is it possible? If yes then how to connect them. Nexys4 DDR will be master device.
  8. Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segm
  9. Hi all. I would like to ask you a question regarding the RAM/DDR controller of the Nexys4DDR. I would like to access (IP parameters in the MIG as in https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-user-demo/start ) the ddr memory whose component is shown below using a 16b width data. For this, if I am correct, the address is handled RANK_BANK_ROW_COLUMN. So I do not understand why in the provided code from Mihaita Nagy they create the user_interface address like these mem_addr <= ram_a_int(26 downto 4) & "0000";
  10. I've done quite a bit of work with using the Cortex A9 on the Zeboard, and as such am at home in the tools flow. I also have a Nexys4 DDR, and need a processor for a project I'm working on...so I figured I'd give the Microblaze a whirl. I did the Hello World tutorial that is on the Digilent site...pretty straightforward, except for one strange bit of behavior: When I run my hello world app, main runs twice, both in debug and release mode. I stepped through the code, and it appears that somewhere in cleanup_platform(), main gets invoked again (recursively). This ends up running ini
  11. I was trying to run echo server example provided on digilent official website. The validation of block diagram is successful also HDL wrapper is successfully generated. Bit file generation is also completed and succefully exported to SDK without error, but while testing program on hardware it do not show any reception of packets. when we ping board status seems to be connected but console window in SDK do not show any details about connection. what are possible causes for error and solutions. console status: ping status: it should be like this:
  12. For a piece of research I am looking to conduct, I am wanting to compare the efficiency of hardware multipliers with different types of designed multipliers. As I have a NEXYS4 DDR, I am looking to use the 25x18 multiplier on board as a basis for comparison. Is there any reference as to what the hardware design is for the on-board multiplier so I have a better frame of reference of what I am comparing to (i.e. is it a Wallace tree multiplier?). --RG
  13. What usb device drivers should be installed? What are their names? Where do they come from? Xilinx? Digilent? Microsoft? Arduino? When I plug nexys4_ddr board into windows 10 computer, it installs FTDI drivers called "usb serial converter" and has two ports A and B These drivers are obviously wrong because the computer makes a sound as if the USB driver is with drawing and reattaching, over and over again. In my experience this is because the board is drawing too much power or the cable is bad. The port works fine with other devices and the cable is the one that shipped with the nex
  14. Hi, I've been having this problem since I got the board and finally decided I want to get rid of it. I'm using a Nexys4 DDR Board and have downloaded the XDC file from the board website. In my projects I've got the board selected in my project settings as you can see. Nevertheless I always get these warnings which are really annoying. They are stating some completely different board and I've got no idea where they are coming from. Does anybody know how to get rid of them? By the way, at the Power tab at Project Summary window it always shows my confidence level as Low. I assume thats because m
  15. Pedro

    Nexys4 DDR & MIG

    Hi, I am trying to understand how to generate a MIG based memory controller in the Nexys4 DDR board, I am reading the UG586 (Memory Interface Solutions), but I am not sure about the system clock and the reference clock. Should I mark them as "no buffer" in the GUI and connect them in the top level source with a 200MHz clock to both of them? Thanks in advance for your help best regards, Pedro