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Found 25 results

  1. I have been following this tutorial and have had no luck. I am uncertain about how to configure the QSPI IP, because the tutorial starts assuming that I have done that part successfully, so I am not even sure if this is the root of my problem. I have tried these two configurations of this IP, compiled them, and exported them to the SDK, and none of them solved the problem: I made sure JP4 is in the QSPI position. On step 3.1 in the tutorial, I can see that the FPGA is programmed successfully and I see the following output (since I chose not comment out the VERBOSE define as suggested in the tutorial): While programming the flash on step 4 I notice that my FPGA code is erased from the board (leds I had assigned to outputs turn off). Is that supposed to happen? At the end of the tutorial I get no "hello world" output on the terminal after resetting the board, though the FPGA does seem to program from the flash successfully, so that portion works, but I can't get the C-code to run from the flash. Here is the sdk_console_output.txt so you can see the steps I took in the sdk to program the board.
  2. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  3. Hi, I am am able to compute the FFT using IP core block available in Vivado 2017. However, whatever is the sample rate of input signal to FFT IPcore, the frequency resolution of the FFT is fixed by clock frequency of the FFT. Example Frequency resolution = sampling frequency/number of samples DDS compiler generates sinusoidal frequency 976.56Hz at a clock freq of 1MHz,therefore the sample rate is 1Ms/s. this signal is given as input to the FFT IPcore 9.0 which is clocked at 5MHz with number of samples as 65536. therefore, Expected frequency resolution = 1MHz/65536, however, measured frequency resolution =5MHz/65536 in Behavioral simulation (Vivado 2017) It does not matter what is the clock frequency of DDS compiler, the frequency resolution of the FFT remains at 5MHz/65536. But, in reality the frequency resolution is fixed by sample rate of input signals and the buffer size of FFT. So, my question is, why in FPGA the frequency resolution is fixed by the clock frequency of FFT rather than sample rate of the input signal. Help is much appreciated. Regards, Subash
  4. Hi, I have been looking on the Digilent site for a while now but I haven't found what the maximum operational temperature of the Nexys Video board is. I use the board to test another in house developed board but I need to run a thermal test at 60°C. Is this possible with the Nexis Video? Kind regards, Oceley
  5. Good morning, I am currently using the uart protocol to communicate my Nexys 4 DDR with Matlab, but I have the inconvenience that I need to send signals of more than 8 bits, someone knows how to receive matrices in vhdl by uart (something like the function fread de matlab). Thank you for your attention
  6. Hello, I'm trying to understand the HDMI capabilities of the Nexys Video Artix-7. I don't own a board yet, so these queries are based on reading spec sheets; please excuse any errors or omissions on my part. The FPGA on the Nexys Video is XC7A200T-1SBG484C, which supports 4 GTP transceivers at 3.75 Gbit/s [1]. However, based on my best interpretation of the Nexys Video data sheet [2] the HDMI ports aren't using the GTP transceivers. The GTPs are used for DisplayPort and FMC connector. Given the HDMI ports aren't using the GTPs, what is the maximum data rate the FPGA can support for them? The HDMI input has an Analog AD8195 buffer, which supports 2.25 Gbps data rate [3]. The HDMI output has a TI TMDS141 buffer, which also supports a 2.25 Gbps data rate [4]. This seems to limit the Nexys to 720p60 or 1080p30, whatever the FPGA may be capable of. Though if these rates are per TDMS channel then that's plenty for 1080p60. However, in the Digilent HDMI demo a video format of 1080p60 is shown [5]. In summary, can someone clarify what video formats and data rates the Nexys Video is capable of on HDMI input and output? Thanks in advance, Will For reference the data rate of some common HDMI formats: 720p60 - 1.45 Gbit/s (HDMI 1.0+) 1080p30 - 1.58 Gbit/s (HDMI 1.0+) 1080p60 - 3.20 Gbit/s (HDMI 1.0+) 2160p30 - 6.18 Gbit/s (HDMI 1.4+) 2160p60 - 12.54 Gbit/s (HDMI 2.0+) [1] (page 50) [2] [3] [4] [5]
  7. Good morning everyone, I am currently developing a computer application in Matlab with help of VHDL and the Nexys 4 DDR, my problem is that I need to send a vector of 16 or more bits through an aurt module, the aurt module only sends 8 bits but I need to send more bits. anyone have any idea how to receive more than 8 bits per aurt? , I know that you should make the matrix reception module in vhdl and I was trying with this module that I have, but it does not work, and I have no idea how to do it to receive matrix. thanks. recepción.txt
  8. Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  9. Hello! I'm newbie in xilinx, and I have one more problem with microblaze with ddr3. I want to have access to DDR3 memory in my MB processor, without processor caches. I implement some design, write very simple code: #include "xparameters.h" int main() { int a = 0; for(;;) { a++; } return 0; } and I can't start debug ... When I start debug, it don't stay at main (but, thread is still running). When I pause it, I see in disassembler what processor stays at _hw_exception_handler In attach you can see system, linker mapping, and problem.. Please help me.
  10. Hello! Where can I find the sourse of demo project for Nexys Video Board? I don't see the archive link on the official website. There is a problem with an OLED display. The official datasheet doesn't have a table of command system. That's why I'd like to have a look at you demo-project. UG-2832HSWEG04-Univision Technology.pdf
  11. Within the schematics of the NEXYS 4 and NEXYS VIDEO boards I couldn't find the part with the Micro-USB JTAG bridge. The part with the FT2232HQ chip is left out in both schematics. Is there a reason for neglecting those parts? Could I find the schematics elsewhere? I'm especially interested in the differences between a combined JTAG and UART Micro-USB solution (as seen on NEXYS 4) and two separate solutions Micro-USB JTAG (1) and Micro-USB UART (2) (as seen on NEXYS VIDEO).
  12. In my lab at work we are using a stash of old Nexys 2 boards for a prototype project. I need to verify the exact part number of the Hirose Fx2 connector, because it's highly embarrassing when you drop $20k on hardware and the cables don't mate. I have looked through the official docs without luck, and appreciate the help. It seems to me it's a FX2-100P-1.27DS. Correct? Many thanks!
  13. MattHollands

    Faulty Nexys 4 DDR?

    Hi, At the start of the year I purchased a Nexyss 4 DDR board from Digilent. I hadn't used it until a few weeks ago, but now am using it for a university project. However, I have discovered two issues with the board while using it. 1. Switch 3 (of the sliding switches), is faulty. The switch will sometimes read as "on", even when the switch is in the "off" position unless it is actively pulled back. I can verify that this is not a coding problem because it happens when the device boots into the default program (loaded by digilent) and all other switches work. 2. Transistor Q8 appears to not be functioning properly. By changing the voltage on the gate I should be able to change the SD cards VDD voltage from 0V to 3.3V, but in reality it is ~2.9V in the off-state and 3.3V in the on-state. I have verified that the gate is swinging from 0V to 3.3V as expected. Issue 1 is not a deal-breaker for me, but issue 2 is a significant deal-breaker as I need the ability to power cycle my SD card. Is this a common issue? It seems to me like this may be due to a faulty board. Matt
  14. Hi, I am looking to buy a board of the Artix-7 family and trying to choose one between Arty, Basys 3 and Nexys 4 DDR. I have the following questions. 1. Is it true that the Vivado software that comes with Arty can only be used for one year since Arty is an evaluation board? 2. Is it possible to install the Vivado software on different computers and work on them (using the same board)? Does this behavior differ in any way among the three boards mentioned above? 3. I am confused about the number of cells in Nexys 4. On Digilent's website, it says Arty & Basys 3 both have about 33K logic "cells", and Nexys 4 has about 16K logic "slices". How many logic "cells" does Nexys 4 have? Which one of these boards can support a larger design? 4. Why does Basys 3 cost more than Arty even though it has less features (like no ethernet, etc.)? Looking forward to your response. This will help me to make a decision. Thank you! P.S.: I had earlier contacted Digilent through the "Contact US" link and asked these questions, but was told some of the questions were too technical, so I need to ask them in the forum. So please help!
  15. Hello everyone, I am using a Nexys 4 DDR for a school project. I am building a system that uses a video camera to detect and track human motion. Several questions: 1. Which port should I use to connect the camera? The immediate one available on the board is the USB host connector, but is it possible to use it to connect a camera? 2. Are there any PMODs available to connect a camera module? 3. Any recommendations for a specific camera model to use for this project? Basically, I need to take the video input, perform some filtering to recognize face and arms, downsample the video and store it in a memory buffer, and output the video real-time to a VGA monitor. Thanks!
  16. My goal is to send data from the fpga to the pc using DSPI. This data, in this case RGB data, gets transformed into video using Unity. There are, however, several problems with sending data from the fpga to pc. Currently the pc is receiving data from the fpga as follows, From the pc side: Open the device (NexysVideo) using the function DmgrOpen(&hif, "NexysVideo") Enable DSPI transfer using the function DspiEnable(hif) Set the SPI mode using the function DspiSetSpiMode(hif, idMod, fShRight) Set the master (pc) clock frequency using the function DspiSetSpeed(hif, frqReq, &pfrqSet) Set the slave select (SS) to the logic 0 state using the function DspiSetSelect(hif, fSel) Receive bytes from the slave (fpga) using the function DspiGet(hif, fFalse, fFalse, bFill, rgbRcv, cbRcv, fFalse), in a while loop There are several things that are not working properly on the pc side, looking at point 3, the SPI mode I would like to use is mode 1, shift data at the rising edge and sample data at the falling edge. However, I can't use mode 1, and currently using mode 0 (sample data at the rising edge and shift data at the falling edge). Another thing is point 4, setting the SCK clock frequency. I noticed that the maximum clock frequency is 30 MHz. When determining the clock frequency, however, using the fpga the clock frequency is about 12 kHz, which is much lower than I would expect! I checked the clock frequency on the pc side using DspiGetSpeed(...) and got 30 MHz, but clearly the fpga receives a lower frequency. From the fpga side: A shift register is connected to the FT2232H IC, I used the diagram on page 14 from for the connection layout The clock from the pc to the FT2232H is connected to the shift register If the slave select (SS) signal is a logic 0, then Every clock cycle a bit is shifted into the FT2232H The ultimate goal is to connect a camera, which outputs raw RGB data to the fpga, and feeds it to the pc. To test if transferring something simple works I continuously send the bitstream "111111110000000000000000", which would get translated to 0xFF0000 or the colour red. This however, does not seem to work, it seems as if the pc and fpga are not in sync. The pc receives values per byte such as (0, 127, 128). Is there something I missed?
  17. Hey all , I am taking a continuous 16 bit serial input from an AFE to nexys 4 ddr board and storing it . Now I have to take this data to pc using usb . I have been searching for this for a long time now (2 weeks to be exact ) but could not find any simple solution . I am using ISE design suite 14.7 VHDL for programming. This is my first fpga project, so please bear my incompetence. Thank you
  18. I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video? when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref Note: some of the setting of my IP MIG In this part i connect the pins R4 and T4 in the CLK_ref_p and CLK_REF_n. but in the synthesis occurs a problem
  19. I am trying to run a microblaze project on the Nexys video development board. However I am having cable driver issues and thus I am attempting to apply the design using a USB host (using a pendrive). I am able to apply a design with simple vivado hardware designs and that works fine. However I cannot get the sdk code for the microblaze to run. Currently I am using the download.bit file generated by the SDK. This bit file is generated using a bootloop. I am following this tutorial ( and so the design should not be the problem. My question is, should the design work if I use the download.bit file generated by SDK (by pressing program FPGA) or should I be using a different bit file to boot from a pendrive? Thanks.
  20. I plan to use Nexys video for image processing. I did a project before where the FPGA gets the data straight from the sensor but now I will be using one of the interfaces (HDMI, USB, etc). There is a number of options, probably any of them valid, I'm just asking for suggestions. The most available cams have USB interface but Nexyx does not have 'pure' USBs unless I'm wrong and I'm not that much willing having an embedded processor just to interface USB to my video format stream. Second thing I though was to use the HDMI input but can't find many cameras with that output... Of course I want to avoid 'pro' and expensive cameras if I can get away with a £20 one. I've seen some USB to HDMI cables (I assume they have some chip somewhere), will they work? Has anybody used them for cameras, not for Pc to Screen? Third I also saw many WiFi cameras, so another option is to add some WiFi module to nexys and connect to the cam that way. As there will be a number of protocols in the middle, again, has anybody tried that before? Last I could just wire the CCD sensor to the I/O through the mezzanine connector, then I wonder why does it deserve to be called 'video' board. Any new suggestion also welcome, thanks guys! John
  21. Peddro

    Nexys3 - MAC address

    Hi guys, does anybody know, how Ethernet on Nexys3 board works? I have read that I can create an ethernet MAC controller via IP core generator in ISEwebpack, but how do I find out the 48bit MAC address of the controller? MAC address is unique and should be assigned by manufacturer, so I think, that it should be hard coded somehow in the board. I apologize for this likely stupid question but I am a beginner in FPGA programming and don't have much experience in this field. Thank you for your answers.
  22. ivan

    Nexys3 VGA output

    Hello everyone. I'm currently trying to create simple VGA EDK project to show something on the LCD monitor with Nexys3 board. Nexys3 board has Micron celular RAM and I have a problem that every row is represented by four same rows on the screen. I think that my problem is like problem described on Xilinx Community forum: I've used PLB bus and tried setting Video Memory on base address of Micron RAM and on high addres - 2 MB. I have also tried to set Video Memory to whole Micron RAM (16 MB). Micron RAM was successfully tested with the SDK built in memory test. For software code, I used example from Xilinx (xtftexample.c). I think that problem is with speed of Micron RAM. I found that in asynchronus mode you need to wait 70 ns for data to be ready. This means that frequency of accessing to Micron RAM is about 14.29 MHz and TFT controller works with clock of 25 MHz. Does anyone have example EDK project which uses Micron RAM in synchronous mode? If you need any information about my project, please let me know. I would appreciate any help.
  23. Hello, The older Atlys boards had a Spartan-6 FPGA which meant the highest progressive resolution supported by the HDMI input and output was 720p (which was always frustrating). I was wondering if that had changed with the newer Series 7 devices like the Zybo or Nexys Video boards? I noticed that hamster was able to get 1080i working. Are SERDES even able to do 1080p theoretically? Thanks for your help! Tim 'mithro' Ansell
  24. logansam

    Nexys FPGA board

    From the album: Nexys FPGA SNES
  25. logansam


    From the album: Nexys FPGA SNES