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Found 2 results

  1. Hello all! I'm trying to get an initial design up and running using the Nexys Video board. According to the specs listed for the board (both here and here), the board supports a 1Gbps ethernet speed, as well as 10/100 Mbps speeds. Looking at the spec for the RTL8211E ethernet chip that I found (is this the right one?), the 1Gbps interface requires 8 transmit data wires and 8 receive data wires working together at a 125 MHz clock. However, if you look at sheet 3 of the schematic for the Nexys Video, there aren't any 8 transmit or receive data wires connected at all, but rather a pair of 4-wire interfaces such as the 10/100Mbps speeds would require. Indeed, it appears as though the only interface connected is the 10/100Mbps interface. Can you confirm for me if this is the case, and if so ... might I suggest you update your description of the board to match the hardware on the board? If not, can you point me at the proper spec for the ethernet chip on board? Thanks! Dan
  2. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture of the the system I obtained at the end but this website would not let me. Any way, my system matches exactly the one in the tutorial. The validation passed, synthesis also passed ( although it gave me the same error the tutorial asked me to ignore, which I did). However, before running implementation I ran a "Report Timing Summary" from the Synthesized Design sub-menu, It gave me the several errors related to the oserdes_clk... To make sure these errors were not caused by something I may have entered wrong while creating the project, I decided to re-do the project starting from a blank slate, but the results were exactly the same in the new project. I tried to paste here an image with the errors but this website would not let me .... Anyway, the errors were Inter-clock paths / oserdes_clk to oserdes_clk / Hold -0.246ns (10 occurrences) Below is one of the Interclock paths that had the Hold timing error From: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK To: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST I think the error is due to a lack of one or more timing constraints. I suspect there might be an error with the board files associated to the Nexys-Video board, specifically related to the MIG7 and the DDR . I do not have enough knowledge of the system to be able to make the constraints myself. How could I solve these timing errors? Thanks