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Found 49 results

  1. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the featured device very very carefully to make sure that it can do what you want it to do. This is not nearly as simple as you would think, especially for ADC devices where specmanship, little white ( sometimes closer to black ) lies, and covering up 'features' that might render the device useless for your requirements has always been the rules of the road. Pore over the schematic for the EMV and trace every pin through the connector to ensure compatibility with your FPGA board. Pay particular attention to power supply pins. Download the supporting software, when available, and understand what you get or don't. Understand that good ADC interfaces, on the analog side, tend to be very application specific. The ADC demo boards tend to be general purpose; but not always. Not listed below is the ADS4449 EVM that I managed to get working with the KC705 board a number of years ago. This 4 channel high speed ADC EVM is set up for narrowband processing of signals centered around 185 MHz. It served it's purpose but I can't recommend it. HSMC compatible boards. ADC/DAC Linear Technology DC2459A LTC1668 16-bit 50 Msps DAC This is one of those rare EVMs designed to connect to an FPGA development board. It can connect directly to a board with an HSMC connector, a DE0 Nano, a Mimas or Mojo board. Mine is always attached to a DE0 Nano and ready to go. I use an external TTL USB UART for control. The DE0 Nano is a cheap and very handy board to have around. ( If only it had a nice Artix FPGA... not that I have anything against the Cyclone V ) Linear Technology DC2390A for LTC2500-32. 2 LTC2500-32 32-bit ADCs and 2 LTC1668 16-bit 50 Msps DACs Connects to any FPGA board with an HSMC connector. The EVM is intended to be used with the Cyclone V SoCkit and has slick software support if used with this ARM based board. I prefer rolling my own interface and using another FPGA platform. Interesting approach o the software side. Terasic makes a couple of not too expensive ADC/DAC HSMC compatible add-on boards. I've already posted a description of a demo project that I completed ( well as far as I need to for now ) recently showing one way to use the Ethernet PHY to make use of such boards. In recent years I've really lost my enthusiasm for low end Intel FPGAs and Quartus tools so that post isn't as silly as you might assume that it is. USB 3.0 Both FTDI and Cypress offer reasonably priced development kit options for using their USB 3.0 interface devices for both HSMC and FMC connector equipped boards. In fact for the FMC versions these are among the only inexpensive mezzanine boards that you will find. I much prefer the flexibility of the Cypress FX3 but be aware that you need to do some embedded ARM development and there's a steep learning curve. If you want to learn about USB this is the way to go. FMC compatible boards. The FMC ecosystem is, with few exceptions, a very expensive place to play in. However on rare occasions you can get lucky. Understand that none of the boards below were intended to connect directly to an FPGA development board. Analog Devices EVAL-AD7761FMCZ AD771 8-channel 16-bit Simultaneous Sampling ADC. I've used this board with the Nexys Video with minimum effort. This is one of those devices where you can be very disappointed if you don't completely understand everything in the data sheet. Analog Devices EVAL-AD7616SDZ AD7616 16-Channel DAS Dual Simultaneous Sampling ADC. This board requires a SDP-I-FMC interposer. I didn't complete a project using it but haven't run into any obstacles hardware-wise. This is another device that requires very careful scrutiny before deciding that you want to spend your time or money on it. ** This advice also applies to FPGA boards that you are thinking of purchasing. If you want to use a particular feature, say DDR, find out if the vendor offers a usable demo showing how you might use it for your project. Find out if you need an evaluation license to build the demo for yourself in order to use that feature. There's only one way to do this... Before making a purchase install Vivado or ISE and see if you can actually build the demo projects for a board. Support, support, support. So what kind of support is provided for the board that you are interested in? Digilent is all over the place here. A very few boards have demo projects with HDL sources. One such board is the Nexys 7-A100T (Nexys 4 DDR) that has an OOB with VHDL sources for most of it's features. It does have a few IP .xco files that are supposed to work with Vivado 2018.2. I was unable to use the sources to generate a bitstream using Vivado 2018.2 SP1. ( I don't have the board so I didn't spend a lot of time trying only because I wanted to look at the DDR IP to reply to a posted question regarding DDR performance. Companies can pretend to offer more support than they really do by offering board design Xilinx IP flow demos. I personally, want to see HDL source as a measure of commitment to a product. Even though Digilent has shown that it's possible; it's hard to mess up an HDL demo. If there's very little in the way of providing build-able demo projects for board features or it take years to provide a reasonably accurate User's Manual these are big red flags. It doesn't mean that the board is useless, just that you had better have the experience and skill, and most importantly for me the time to write your own interfaces Tips for beginners. Not everything that board or even IC vendor makes is wonderful. If they spent money developing a product then they sure will try to find a customer to pay for those development costs. Sometimes, the only way to identify the dirty little secrets is to observe what's missing in a data sheet or sales blurb. If a normal feature is usually highlighted for most similar products and noticeably absent for the one that you are eyeing then this is a big red flag. What's missing is sometimes more informative than what's stated.
  2. Ruskuls

    Nexys Video HDMI in problems

    Hello, First question at this forum I'm using Nexys Video FPGA dev board. Receiving input video stream via HDMI, saving it on DDR3 memory, reading back and transmitting over HDMI. Design works, tested with different resolutions etc. But today I powered my Nexys video board and computer didn't find any connected HDMI, even worse, HDMI from PC could't detect any monitor. I suppose it's broken. Consulted with my collegues and same problem appeared with them - twice. My question, did any of you experienced same problem? if Yes, did You solved it and how. Thanks in advance! Rinalds P.S. I'm using Intel(r) HD 4600 graphics card, updated drivers & restared PC
  3. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The only downside for Version 1 is that you need a Digilent ATLYS board to serve as the test platform. [Edited] Not 4 hours have passed and I found a silly bug that mis-reported packet size. I've replaced the archive. I also forgot to add the teaser: Wed Oct 17 16:13:03 2018 test_interval_reg = 0x000000000100 >>> Starting test Payload Size = 65536 Total Number of TEST Packets sent = 60000 Total Number of TEST Packets received = 60000 Total Number of TEST Bytes sent = 3932160000 Total Number of TEST Bytes received = 3932160000 Total Number of Errors = 0 Total Number of PHY rxerr Events = 0 Total Duration of the test (in Seconds) = 31.585437952 Percentage Errors = 0.0 TEST packets sent per second = 1899.60956347 Tx Data Rate (Bytes/s) = 124492812.352 Rx Data Rate (Bytes/s) = 124492812.352 ETHERNET_PHY_TESTER_Release_V1A.zip
  4. Hello, I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning: [Timing 38-282] The design failed to meet the timing requirements. According to the Timing Report this warning refers to the Path from "hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C" to "hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D" with source clock mmcm_clkout1 and destination clock dvi2rgb_0_PixelClk. The reported slack is -0.787. Any timing constraints of this should have been provided by Vivado automatically, so what could I do about this warning? I tried this on three different machines, always getting the same critical warning. Eff
  5. Hello. I am a beginner in FPGA. Also I am poor in English. Sorry. I am developing with Nexys Video. Although the design is complete, I am suffering from using QSPI Config and e-FUSE security together. I tried QSPI Config first. This worked well. Next I tried e-FUSE security. I wrote the security key and finished setting the FUSE register, After that, I could not program the QSPI. When executing the program, the following error will be displayed and will be aborted. -------------------------------------------------------------------- [Labtools 27-3165] End of startup status: LOW -------------------------------------------------------------------- You can not configure from QSPI, but you can configure an encrypted bit / bin file using JTAG. I replaced the USB cable with reference to the past forum, but there was no effect .... What does this error mean? Is there a solution for using QSPI Config and e-FUSE security together? Please tell me if you need information to solve the problem. Thank you koseki.
  6. miezekatzen_dompteur

    Simple HDMI Output Nexys Video Board

    Hello, i have got a problem with the output of a simple HDMI signal. I use the the IP block rgb2dvi of digilent and a vga.vhd file which creates the hsync, vsync signals. I connected the signals with vid_pHSync, vid_pVsync of the rgb2dvi IP. I created a vector (23 downto 0) with ('1') for vid_pData, with this vector is want show a white picture on the screen. The vid_pVDE is connected with '1'. I used the vga.vhd in a former project where i created a VGA signal on a screen. The vga.vhd creates a signal with 800 x 600 pix and 72Hz. The pixel clock is 50Mhz. What's the meaning of the vid_pVDE signal...?? My problem is that i dont get a signal on the screen...?? Have a nice day...Bye bye project_6.srcs.zip
  7. AdamZ

    Nexys Video No Hardware Target Exists

    I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  8. hardlyhacker

    nexys video out-of-box ethernet not working

    Hi, I just got nexys video and was going down the list of out-of-box demo at the bottom of its reference manual : https://reference.digilentinc.com/reference/programmable-logic/nexys-video/reference-manual When I connect the ethernet cable, ACT/LINK/USER LEDs blink for a bit, then LINK/USER blink in sync indefinitely, but there's no IP address displayed on OLED screen, just shows 0.0.0.0 I tried checking things on my router side (Netgear), but there is no indication of the device in its logs. Are there any way to confirm that the ethernet is working properly?
  9. Ben_Cook

    Nexys Video HDMI Demo boot from QSPI Flash

    Hello, I have a Nexys Video board and I have successfully loaded the “Nexys Video HDMI Demo”. I followed the tutorial "Using Digilent Github Demo Projects" to install and run the project through Vivado and SDK. I would like to learn how to get this demo to boot from QSPI flash following initial application of power to the board. I tried to follow this tutorial “How To Store Your SDK Project in SPI Flash". However, I get stuck creating the bootloader at step 1.2 as I do not have the option to use the ‘SREC SPI Bootloader’ template. When I try to select SREC SPI Bootloader, the SDK throws the following error: “This application requires a AXI Quad SPI in the hardware.” At this point, the ‘Next’ and ‘Finish’ buttons are greyed out, so I hit a dead-end. Could you please advise how I would go about storing this demo in SPI Flash? Many thanks in advance, Ben Cook
  10. Hi, I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP. The AXI Uartlite is configured as follows. CLK 1MHz, baud rate 9600, data bits 8 S_AXI_wvalid <= '1'; S_AXI_wstrb <= '1'; S_AXI_awvalid <= '1'; S_AXI_aresetn <= '1'; S_AXI_awaddr <= "0100"; S_AXI_wdata <= "00000000000000000000000001010011"; When I simulate, the TX port output of AXI Uartlite just remains ‘X’ state instead toggling as per S_AXI_wdata. I have simulated upto 4 seconds and ll the values are initialized from the beginning of simulation. Am I missing any configuration setting? or anything needs to be carried out to get teh data at TX port ? Help is much appreciated. Regards, Subash
  11. Hi, I have been looking on the Digilent site for a while now but I haven't found what the maximum operational temperature of the Nexys Video board is. I use the board to test another in house developed board but I need to run a thermal test at 60°C. Is this possible with the Nexis Video? Kind regards, Oceley
  12. Souradeep Mitra

    CMOS signals on Nexys Video FMC

    In the Nexys Video Artix 7 board the FMC connector contains 34 differential pairs connected to the FPGA. Can I use two tracks of a differential pair as two single ended CMOS signals. Also can I configure LVDS pins and CMOS pins on a single I/O bank of the FPGA?
  13. Hi, I tried the example project named Nexys Video XADC Demo present at the resource center. Before programming the FPGA, the voltage values of AD1, AD0, AD8, and AD9 are very low (20mV) w.r.t the ground. If the FPGA is programmed, the voltage of AD1, AD0, AD8, and AD9 jumps to 0.4V, even without any input to them (ADC pins are kept open). Besides, after programming, if i provide 500mv unipolar sine signal to just AD1, the sine signal is appearing at other pins such as AD0, AD8, and AD9. I am not able to understand the reason behind the voltage jump and why the signal given at one ADC appears at others before and after programming the FPGA. Help is much appreciated. Regards, Subash
  14. Hello, I'm working for minimalizing Nexys Video to small board that has only video processing feature. And, I have found some unconnected pins with other pins in Nexys Video Schematic. Those pins are this: - HDMI_RX_PEEN in Sheet 6 - PROG_* pins on BANK 14 in Sheet 10 - T3 pin on BANK 34 in Sheet 11 Are these pins black box? (especially PROG pins) If I ignore these pins, will there be a problem?
  15. I'm using the Nexys Video board and I'd like to use the FIFO capability of the FTDI chip (IC13 connected to J12) to get data from the FPGA quickly and easily while keeping the JTAG lines high-impedance. I would like to use the FT2232H FIFO port while using our own JTAG (J17). The JTAG lines on that chip are high impedance until the USB cable is plugged in and I'd like to keep them high impedance while using the USB port. If you don't know, can you send me the schematic page for IC13/J12?
  16. wangjianli

    nexys video HDMI Demo

    Hello, My FPGA board is nexys video,vivado is 2016.4, I Download and Launch the Nexys Video HDMI Demo,It have an error when generating a bit file,How to solve it? thanks Ali
  17. I used Nexys Video Board for image processing via HDMI Interface. And now i need to make small this board. For this work, I drew the schematic based on the Nexys Video Board's schematic. But i'm a beginner in this field, so i couldn't find exact information to some element. Those elements are this: 1. What does Foot and SHIELD in schematic Sheet 1 means? 2. Some pins could not find the pin connected together Those pins are this: - HDMI_RX_PEEN in Sheet 6 - PROG_ pins on BANK 14 in Sheet 10 (PROG_RDN, PROG_WRN, PROG_D0/SCK, PROG_CLKO, PROG_TXEN, PROG_D3/SS, PROG_D1,MOSI, PROG_SPIEN, PROG_D6, PROG_RXEN, PROG_SIWUN, PROG_D2/MISO, PROG_D7, PROG_D5, PROG_D4) - T3 pin on BANK 34 in Sheet 11 3. There are elements that can't know exact name. - HDMI connect in Sheet 5. (There is comment written HDMI-47151 but i found similar devices: 47151-0001, 47151-1001 etc.) - All of Registers, Capacitors, Ferrite Beads, Jumpers, Switches and LEDs. Because I don't have experience about pcb design, I can't find exact element so i want to see BoM of Nexys Video Board
  18. hello, The following is my description of the problem: I use the FPGA board is nexy Nexys Video A7 board, want to achieve usb and PC information transmission, want to use the synchronization fifo mode,I used FTDI software (FT_Prog.exe) to eeprom into 245fifo mode, but vivado since then show the link is not the device, bit file can not be written. I have two the same board, another board did not eeprom configuration before, vivado can link to the equipment, but after the configuration also appeared in this issue, is not my configuration eeprom there is a problem?Here's my screenshot of the problem。 I hope you will solve this problem for me。 wang
  19. The "Nexys Video™ FPGA Board Reference Manual" (Revised May 30, 2017) describes in Table 9 (page 20) the "Recommended usage" of the pins of JXADC with "LVDS_25 input/output" (with V_ADJ=2.5V). However, the discussion in has led to the result that LVDS-standard is not supported without changing the board. I would recommend to change the reference manual at this point. The documentation should clearly name supported standards especially if it is targeted to students that may not know all details of the IO-standards. The best way of a replacement of "LVDS" would be a list of IO-standards that work on this connector without changing the board. If the list is too long (the list of standards supported by Artix-7 fills several pages) it can be moved to the appendix. The minimal solution would be the replacement of "LVDS" by "differential" and let to the user/student to find out if a certain standard can be implemented with the board. Btw. There is a small typo in the table: The 3rd differential pair of JXADC is 3-9 (according to the schematic).
  20. Hello! I use Nexys Video board and plan to use a Pmod connector with LVDS standard (input and output). Following the reference manual, the only Pmod connector that provides LVDS (LVDS_25) for input and outputs is JXADC (with V_ADJ=2.5V). This connector is equipped with 100 ohm series resistors. The Xilinx documentation UG471 (v1.8, pages 91-93) does not describe that series resistors are recommended or required. Is it possible to use Pmod connector JXADC for LVDS inputs and outputs with that board? Or must I short cut the series resistors (R42-R45/R47-R50)? Many thanks in advance!
  21. Hello all! I'm trying to do some work with a Nexys Video board, and came across an error regarding the voltage standard of the DDR3 SDRAM and the CPU_RESETN line. According to the schematic, these two wire sets (on the same bank) are at 1.5V. According to the master XDC file, however, the CPU_RESETN line is listed as 1.2V. According to the board definition file, the DDR3 lines are 1.5V's. Can you tell me which is is? Thanks! Dan
  22. Turn your Nexys Video board into something useful for hardware development by adding the IO capabilities of another FPGA board. In this project the other board is a Digilent Spartan 3A Starter board. But it has a lot of resources that make it useful for a variety of projects needing an FPGA. The "magic" is supplied by those wonderful Ethernet PHY modems. Release 3 offers two target boards, Gigabit and 100 Mbps designs. Check it out even if all you want to do is connect any two FPGA boards with Ethernet capability. IO_EXPANDER_R3.zip
  23. wallento

    DPTI: Synchronous Interface and JTAG

    Hi everyone, I have started using the Nexys Video board and have a question about DPTI before starting: I understand that when channel A is used in synchronous FT245 mode in the FT2232 chip that channel B is switched off. Is that correct? That would mean I cannout use synchronous DPTI in parallel with Vivado debugging, right? One alternative is using asynchronous mode apparently, but I am also wondering if I could connect my debug cable to the unequipped JTAG port instead? Anyone tried that setup? Cheers, Stefan
  24. I'm using the Nexys Video board, and I followed https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-programming-guide/start this tutorial and use JTAG to program it. However, data and program are lost when power is off and I have to re-configure the board. What should I do to have the program launched automatically every time the power is on? Through the tutorial mentioned above, I understand that I need a Quad SPI Flash, should I just follow the section N°5? By the way, once the program is stored, how to modify? If I use a QSPI flash, do I just need to create a new bitstream and repeat the instructions in section n°5?
  25. hamster

    DisplayPort implemented.

    I've finally broken the back of DisplayPort, and have a 800x600 colour bar picture showing using my Nexys Video. Still a lot of work to go before I get UHD resolutions working and a nice generic interface, but all the low-level base technology stuff is working. I started on August 12th, so it has taken over a solid month of hobby time to get this far! Source is on Github at https://github.com/hamsternz/FPGA_DisplayPort and some notes are on my Wiki at http://hamsterworks.co.nz/mediawiki/index.php/DisplayPort Currently sits at about 9,000 lines of VHDL... but only needs 610 LUTs and 680 flipflops.