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  1. I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCCReceive the TMDS signalsDe-serialize them into 10-bit symbolsAlign the symbols using bitslipsTune the input delays for best receptionConvert the TMDS symbols into data valuesExtract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs)Extract Video Infoframes from the ADP dataExtract Audio Samples from the ADP data.Extract Raw Pixels from the VDPsPerform 422 to 444 conversion, if required
  2. Hi, I followed the instruction in carefully to create the simple echo server with Nexys video board. The vivado version is 16.2. The Ethernet licence is evaluation version. After creating echo server application and run with SDK , it does not run as expected, the output is as follows: -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence
  3. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the feat
  4. Hello all, I've been working on an audio looping project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also
  5. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high t
  6. I am a longtime Actel user in VHDL and want to begin using Xilinx FPGAs. The Nexys Video board looks attractive, but looking at the information on-line I cannot answer some fundamental questions. Does this product include a target specific version of the development environment that allows for design in VHDL? My application needs to use FFTs but I cannot figure out what the utilization per instantiation will be in this device and how much, if any, it will cost for the FFT IP that I can use with this board. Apart from a host computer, what else must I buy to be able to develop VHDL and test
  7. Hi, I am playing with the nexys video user demo. I have changed the bitstream to display an overlay (BITC) instead of mouse pointer, and I can bake the bootloader into the bitstream and write it to the flash. I now want to change the microblaze software, which appears to be at flash address 0xa00000. What format image do I write there? Is it the ascii SREC file? James
  8. Is there an example project on how to interface with the SD card slot on the nexys video board? I’m working on a project to decode a .wav file from an sd card to output to the audio codec.
  9. Hi - Looking to use the rgb2dvi_V1_2 module to get video into the FPGA. Vivado is unhappy with TMDS_Encoder.vhd Line 90, as folows: function sum_bits(u : std_logic_vector) return unsigned(3 downto 0) is Generates the following error: ERROR: 'indexed name' is not a type Any ideas on how to fix that? Many thanks, IanM
  10. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into t
  11. I setup my Nexys Video for the first time, and tried to setup an echo server using Vivado/SDK. I followed the following tutorial: When I go to generate a bitstream, I get the following error: [Common 17-69] Command Failed: This design contains one or more cells for which bitstream generation is not permitted: design_1_i/axi_ethernet_0_U0_mac_U0/tri_mode_ethernet_mac_i/bd_929b_mac_0_tri_mode_ethernet_mac_v9_0_12) If a new IP Core license was a
  12. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The
  13. Hello All, I am currently working on Nexys Video Ethernet. I want to transmit and recieve UDP packets between PC and Nexys Video FPGA . Is it possible to perform without Microblaze? How to send UDP Packets from PC to FPGA.?
  14. Hello, First question at this forum I'm using Nexys Video FPGA dev board. Receiving input video stream via HDMI, saving it on DDR3 memory, reading back and transmitting over HDMI. Design works, tested with different resolutions etc. But today I powered my Nexys video board and computer didn't find any connected HDMI, even worse, HDMI from PC could't detect any monitor. I suppose it's broken. Consulted with my collegues and same problem appeared with them - twice. My question, did any of you experienced same problem? if Yes, did You solved it and how.
  15. Hello, I downloaded the latest release of the "Nexys Video HDMI Demo" from Github ( and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning: [Timing 38-282] The design failed to meet the timing requirements. According to the Timing Report this warning refers to the
  16. Hello. I am a beginner in FPGA. Also I am poor in English. Sorry. I am developing with Nexys Video. Although the design is complete, I am suffering from using QSPI Config and e-FUSE security together. I tried QSPI Config first. This worked well. Next I tried e-FUSE security. I wrote the security key and finished setting the FUSE register, After that, I could not program the QSPI. When executing the program, the following error will be displayed and will be aborted. -------------------------------------------------------------------- [Labtools 27-3165] End of startup
  17. Hello, i have got a problem with the output of a simple HDMI signal. I use the the IP block rgb2dvi of digilent and a vga.vhd file which creates the hsync, vsync signals. I connected the signals with vid_pHSync, vid_pVsync of the rgb2dvi IP. I created a vector (23 downto 0) with ('1') for vid_pData, with this vector is want show a white picture on the screen. The vid_pVDE is connected with '1'. I used the vga.vhd in a former project where i created a VGA signal on a screen. The vga.vhd creates a signal with 800 x 600 pix and 72Hz. The pixel clock is 50Mhz. What's the me
  18. Hi, I just got nexys video and was going down the list of out-of-box demo at the bottom of its reference manual : When I connect the ethernet cable, ACT/LINK/USER LEDs blink for a bit, then LINK/USER blink in sync indefinitely, but there's no IP address displayed on OLED screen, just shows I tried checking things on my router side (Netgear), but there is no indication of the device in its logs. Are there any way to confirm that the ethernet is working properly?
  19. Hello, I have a Nexys Video board and I have successfully loaded the “Nexys Video HDMI Demo”. I followed the tutorial "Using Digilent Github Demo Projects" to install and run the project through Vivado and SDK. I would like to learn how to get this demo to boot from QSPI flash following initial application of power to the board. I tried to follow this tutorial “How To Store Your SDK Project in SPI Flash". However, I get stuck creating the bootloader at step 1.2 as I do not have the option to use the ‘SREC SPI Bootloader’ template. When I try to select SREC SPI Bootloader, the SDK throws
  20. Hi, I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP. The AXI Uartlite is configured as follows. CLK 1MHz, baud rate 9600, data bits 8 S_AXI_wvalid <= '1'; S_AXI_wstrb <= '1'; S_AXI_awvalid <= '1'; S_AXI_aresetn <= '1'; S_AXI_awaddr <= "0100"; S_AXI_wdata <= "00000000000000000000000001010011"; When I simulate, the TX port output of AXI Uartlite just remains ‘X’
  21. Hi, I have been looking on the Digilent site for a while now but I haven't found what the maximum operational temperature of the Nexys Video board is. I use the board to test another in house developed board but I need to run a thermal test at 60°C. Is this possible with the Nexis Video? Kind regards, Oceley
  22. In the Nexys Video Artix 7 board the FMC connector contains 34 differential pairs connected to the FPGA. Can I use two tracks of a differential pair as two single ended CMOS signals. Also can I configure LVDS pins and CMOS pins on a single I/O bank of the FPGA?
  23. Hi, I tried the example project named Nexys Video XADC Demo present at the resource center. Before programming the FPGA, the voltage values of AD1, AD0, AD8, and AD9 are very low (20mV) w.r.t the ground. If the FPGA is programmed, the voltage of AD1, AD0, AD8, and AD9 jumps to 0.4V, even without any input to them (ADC pins are kept open). Besides, after programming, if i provide 500mv unipolar sine signal to just AD1, the sine signal is appearing at other pins such as AD0, AD8, and AD9. I am not able to understand the reason behind the voltage jump and why the signal given a
  24. Hello, I'm working for minimalizing Nexys Video to small board that has only video processing feature. And, I have found some unconnected pins with other pins in Nexys Video Schematic. Those pins are this: - HDMI_RX_PEEN in Sheet 6 - PROG_* pins on BANK 14 in Sheet 10 - T3 pin on BANK 34 in Sheet 11 Are these pins black box? (especially PROG pins) If I ignore these pins, will there be a problem?
  25. I'm using the Nexys Video board and I'd like to use the FIFO capability of the FTDI chip (IC13 connected to J12) to get data from the FPGA quickly and easily while keeping the JTAG lines high-impedance. I would like to use the FT2232H FIFO port while using our own JTAG (J17). The JTAG lines on that chip are high impedance until the USB cable is plugged in and I'd like to keep them high impedance while using the USB port. If you don't know, can you send me the schematic page for IC13/J12?