Search the Community

Showing results for tags 'nexys 4 ddr'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 27 results

  1. Vonmuller

    Custom Function Generator

    This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  2. Kopart

    Nexys 4 DDR with a new DDR2 chip

    We have 4 Nexys 4 DDR boards with the same "Rev C" revision. I have compiled .bit file with MIG IP settings based on Digilent example "Nexys 4 DDR Xilinx MIG Project" in Vivado 2018.1 The fist two boards have MIRA DDR2 chip and DDR calibration complete successfully with this .bit file The second two boards has ISSI DDR2 chip and DDR calibration fails with the same .bit file. What are the MIG setting differences for these DDR2 chips?
  3. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  4. Hello, I am following this tutorial for microblaze for the nexys 4 ddr: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start?redirect=1 I am getting an error for the mig_7_series... generation that is outlined when I try to generate the bitstream in step 14. It looks like it is pulling the mig from Xilinx's core generation, is it supposed to be using the mig from the nexys 4 ddr files instead? Here is my error output: Another thing to note, I have a space in the directory path, is that the issue possibly? It is not complaining about anything else though. I have also verified that the file it "can't find" is actually there and has contents. I'm running Vivado 2017.4 WebPack, but I can't imagine this would cause issues for a Xilinx IP core, maybe for IP cores from Digilent. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 . error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.4/data/ip/xilinx/mig_7series_v4_0/xit/synthesis.xit': error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s). ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_mig_7series_0_81M .
  5. Dalin

    NEXYS4 DDR with Xilinx ise 14.7

    Hello Is it possible to program NEXYS 4 DDR using Xilins ISE 14.7 Thank you
  6. Hello, I have a Nexys 4 DDR board and I was going through the tutorial. I installed the suite and when I reach the point to connect the target, Vivado is unable to find it. The jumper of the JTAG is right and I tried more than one USB cable. The error I get on Vivado is "No hardware targets exist on the server [TCP:localhost:3121]" Your help is appreciated. Ahmed
  7. I need to read the temperature of the FPGA using the temperature sensor on board ADT7420. Is there any demo to show how to read out the result from the sensor?
  8. Hello. I have to adjust the speed (baud), parity bit (if I want), stop bit. For both software alike. I would like to know if anyone has that code in VHDL / VERILOG ? (UART/JTAG)
  9. Hi. I would like to know, if it is possible to modify the sampling frequency, the number of samples of the ADC of the card Nexys 4 DDR ?. I know there are modes of use, but these depend on the registers but do not allow manipulation of these parameters. If you can, I would be grateful if you could tell me how it is possible.
  10. To allow software developers to be able to easily get the computational benefits of FPGAs we created Hastlayer: it turns software written for the .NET platform into an equivalent (VHDL) hardware description. It does this while also handling everything in the background to allow the usage of the resulting hardware in the same way as the original software was run - basically where there was a function call there's still a function call but now it really executes on an FPGA, as logic hardware. Here's a demo video of how it works: And why do I post it here? You can also see from the above thumbnail that you can use Hastlayer with Nexys 4 DDR boards! Connecting the board to a host PC via USB as well as Ethernet is supported. You can even use multiple boards simultaneously if you use the latter. Do you own a Nexys 4 DDR? You can get access to Hastlayer, just ask! (And you can get access to it otherwise too!)
  11. Zoltán Lehóczky

    Nexys 4 DDR shows up with two COM ports

    We use Nexys 4 DDR boards for testing our platform. While with most of the Windows host PCs there are no issues, with one of our clients' when the board is plugged in (using the supplied micro USB cable) it shows up as two COM ports under Windows's Device Manager. We suspect this is behind that we can't properly run Xilinx SDK programs on the board, the debugger looses the connection. Is it normal that the board shows up as two COM ports? (When the board is de-attached the ports disappear, so both are surely the single board.) If yes, can this cause issues? If now, how can we begin to troubleshoot the problem, what can possible be behind it? Thank you in advance!
  12. Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick
  13. Vonmuller

    Ethernet UDP echo-server

    A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: 192.168.1.10 Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use any input or output FIFO's as elesticity buffers,both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes, which allows better resource utilisation at the price of, probably, more complex design architecture. Design is implemented in VHDL using ISE by Xilinx. Below there are the source files for the echo-server projects along with .m file to transmit/receive data using MatLAB. Figure "wireshark_capture" illustrates the data traffic between FPGA board and data server (MatLAB); Figure "TxRx_Error" compares transmitted data against the data received from the board. UDP echo-server manual.7z UDP echo-server.7z
  14. Hello all, I'm trying to implement Microblaze server on Nexys 4 DDR. Design steps are provide on official website, i follow same procedure as mention on website but while generating Bitstream following error pop up and synthesis failed. please suggest possible errors in design and modification to be done to block diagram. I have attach snap of error message and Block diagram below. PFA, Thanks in Advance Regards, Kumar Khandagle.
  15. Hello ! I'm currently encoutering an issue about how to assign each digit of a number on the seven segment display. For example, if I have the number 1932, how to affect the '2' on the first digit display . The '3' on the second, the '9' on the third, etc... Actually, I have a 4-bit BCD (which functions) and I want to display the decimal number. My output, bcd0, bcd1, bcd2, bcd3 represents the ones, the tens, the hundres and the thousands). I'm decoding each output like that : case bcd0 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd1 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd2 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd3 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; Of course, I know that I have to activate the 4 first anodes (low level). And that I have to assign each bit of "seven_seg" to the good pin on the .XCF file. Thank you very much for help !
  16. Hello ! I'm currently working on a project which consists in designing a digital lock-in amplifier on a FPGA board. For this, I am using a Nexys 4 DDR and an Analog Device's ADC (EVAL AD7984 PMDZ). My first goal is to interface properly the ADC component with the FPGA using a Pmod port. I have some basics knowledge about the use of Vivado so that's why I am asking you about this. I followed the tutorials about "getting started about MicroBlaze" to follow then "using Pmods IP". My question is : When I followed the first tutorial mentionned above, we created a a basic Microblaze block design. Do I have to use all this design or is it possible to do easier ? And, do I have to design it with MicroBlaze or can I just write some VHDL code ? I want in a first part, to give a signal input in the ADC and then, light a LED on the board to confirm that the FPGA is well connected with the ADC. Can you, please, give me a plan to achieve my goal ? I don't ask for a solution, I want to manage it by myself, but just some help to know what are the steps I have to follow. Thank you very much ! Have a good day !
  17. Lawrence

    Nexys 4 DDR memory part mismatch

    Hi everybody, I've just received my shiny new Nexys4 DDR board and I've noticed that the DDR2 part is different than that mentioned in the Reference Manual and the schematics which is Micron MT47H64M16HR-25:H. My board (Revision C) has a Mira P2R1GE4KGF - G8E chip. At a cursory read of the data sheets it looks similar to the "original" Micron chip but may not be exactly the same. I'm a newbie here and not experienced with the subtleties of the DDR specifications. My purpose is to learn as much as I can by using the provided examples not to match data sheets Are these chips the same thing? If the chips differ please provide the correct settings for the MIG wizard and any other related material(ucf, xdc, ram2ddr etc.). An official correction or clarification of the documentation would be very appreciated too Thanks a lot, Lawrence
  18. Hi all, I am using a Nexys 4 DDR board to interface microSD and microSDHC cards using the SPI mode. (For those interested in what the whole thing is all about, click here.) Might it be, that microSD cards are needing current in the range of 10mA (e.g. look at Transcend's 2GB SD card datasheet - link) and microSDHC (SDHC vs SD) are needing 10x of this, e.g. look here at Samsung's 32GB SDHC card: http://www.singerphoto.co.za/SingerPhotographicOnlineDocuments/WebImages/SellSheetPDFs/mesamp64a.pdf How much current is the Nexys 4 DDR SD Card slot able to supply? The first card I wrote about above (Transcend's 2GB SD V2 card) works fine with my controller, the second card (Samsung's) is not even initializing (no response to CMD0). (Some other SDHC cards are working with my controller, see below.) Are there some settings I need to do in the UCF file, e.g. fast SLEW rate or another value for DRIVE (to supply more current)? Currently my UCF file looks like this: ##Micro SD Connector NET "SD_RESET" LOC = E2 | IOSTANDARD = LVCMOS33; NET "SD_CLK" LOC = B1 | IOSTANDARD = LVCMOS33; NET "SD_MOSI" LOC = C1 | IOSTANDARD = LVCMOS33; NET "SD_MISO" LOC = C2 | IOSTANDARD = LVCMOS33 | PULLUP; Here is the source (Link) of my controller. I tested it with ~40 cards. 20 of them are SD cards Version 1 and Version 2 (from 64 MB up to two GB): Works fine and stable with all of them. 20 of them are SDHC. When it comes to SDHC, it works with about 50% of the cards (well - works kind of: I need to reset after each read command). The other 50% are showing really strange behaviours: Some are only reporting themselves as a SDHC during the coldstart/hard reset (insert card) and from then on "claim" to be a SD V2 card, others are initializing well but when it comes to reading, they never send a R1 on READ_BLOCK, etc. While googling I found some comments in forums, that strange behaviour might be rooted in a lack of current, so this is the background of my question. Best regards Mirko
  19. Hello, I want to feed video from my smartphone camera to Genesys and want to display the video on the PC. I don't know how to interface. How should I connect my smartphone camera with Genesys board? I also want to do the same thing with Nexys 4 DDR board. Any kind of information will be helpful. Thank You.
  20. Tapish

    read files from Nexys 4 ddr using usb

    Hey all , I am taking a continuous 16 bit serial input from an AFE to nexys 4 ddr board and storing it . Now I have to take this data to pc using usb . I have been searching for this for a long time now (2 weeks to be exact ) but could not find any simple solution . I am using ISE design suite 14.7 VHDL for programming. This is my first fpga project, so please bear my incompetence. Thank you
  21. Ghinda

    Analog read with Nexys4 DDR

    Hello! I have a Nexys 4 DDR. I'm trying to use an analog sensor like this: https://www.sparkfun.com/products/10264. I want to read data from it with a Nexys 4 DDR but I don't know how to do it. I have tried to read this document: http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf but I didn't understand how to do it. I use Vivado and VHDL. Can someone help me? Thank you!
  22. Have anyone tried successfully to run the advanced I/O demo on nexys DDR ? https://reference.digilentinc.com/nexys4-ddr:userdemo I follow the instruction to create the project, when I run synthesis, it just cannot stop in the procedure.... I got three warnings. WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/PxlClkGen/PxlClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ClkGen/ClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products cant be done. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/ddr/ddr.xci Run output log is uploaded. runme.log
  23. PartyArty

    Nexys 4 DDR always is busy

    Just got a Nexys 4 DDR board for a class and the second I plugged it in, the busy light came on and it hasn't gone off yet and I get a message in Vivado when trying to connect it to the hw_server saying it may be locked by another hw_server?
  24. Alex

    Slow synthesis and implementation

    A professor is going to switch from Spartan 3 to Nexys 4 DDR. He comes up the following problem. We’re still experiencing significantly longer synthesis/implementation times in ISE for Artix-7, compared to Spartan 3. I also tried the designs in Vivado, with similar results. This does depend a lot on the CPU in the computer running the software. My laptop (Intel Core i7) took 3:45 to do synthesis through place and route, whereas it took 9:26 in the lab and my desktop PC (Intel Core2 Quad Q8400). Add additional time for generating a configuration file. The Nexys4 sample project took over 13 minutes for implementation on my office PC. If there are any project options that you know of that would shorten this time, we would love to try them out. I have tried changing “Flow_RuntimeOptimize” to “Flow_Quick”, but for simple designs this only cut off a couple of seconds.
  25. Hi, I am a beginner of ethernet design. I got a small project published on this website: http://www.fpga4fun.com/10BASE-T0.html . I have successfully updated MAC address, IP, etc... But I have no idea how to set constraint file in ISE. Through reading the Nexys 4 DDR manual, I guess I need an extra clkIn for this project to work on the board, so I created two clocks: one is for D5, CLKIN, 50MHz, and another is for the project, 20MHz. and I set the pin number in the project below. NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; NET "clk" TNM_NET = sys_clk_pin; NET "Ethernet_TDp" LOC=A9 | IOSTANDARD=LVCMOS33; NET "Ethernet_TDm" LOC=C9 | IOSTANDARD=LVCMOS33; A9 is connected to MDIO, and C9 is connected to MDC. But I cannot see any data flow from PC to the board using the software provided by that website. Can anyone help me set the constraint file? Thank you!