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  1. Hi Digilent, My Nexys 4 DDR couldn't be powered on and I found that the IC20 on board was disappered. However, I can't find this chip in the schematic. Could you let me know this IC's type and I will buy it to repair board myself. Thanks
  2. Hello, I have a Nexys 4 DDR board and I was going through the tutorial. I installed the suite and when I reach the point to connect the target, Vivado is unable to find it. The jumper of the JTAG is right and I tried more than one USB cable. The error I get on Vivado is "No hardware targets exist on the server [TCP:localhost:3121]" Your help is appreciated. Ahmed
  3. Hello all. I'm a newbie to Vivado HLS (2018.3) and trying to add the Nexys 4 DDR board files in a new project, and it's not in the Device selection dialog list. I placed the board files in "Xilinx\Vivado\2018.3\data\boards\board_files" and it's there in Vivado, but not in Vivado HLS. How can I add the board files to Vivado HLS? Thank you!
  4. This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. No
  5. We have 4 Nexys 4 DDR boards with the same "Rev C" revision. I have compiled .bit file with MIG IP settings based on Digilent example "Nexys 4 DDR Xilinx MIG Project" in Vivado 2018.1 The fist two boards have MIRA DDR2 chip and DDR calibration complete successfully with this .bit file The second two boards has ISSI DDR2 chip and DDR calibration fails with the same .bit file. What are the MIG setting differences for these DDR2 chips?
  6. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code...
  7. Hello, I am following this tutorial for microblaze for the nexys 4 ddr: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start?redirect=1 I am getting an error for the mig_7_series... generation that is outlined when I try to generate the bitstream in step 14. It looks like it is pulling the mig from Xilinx's core generation, is it supposed to be using the mig from the nexys 4 ddr files instead? Here is my error output: Another thing to note, I have a space in the directory path, is that the issue possib
  8. Hello Is it possible to program NEXYS 4 DDR using Xilins ISE 14.7 Thank you
  9. I need to read the temperature of the FPGA using the temperature sensor on board ADT7420. Is there any demo to show how to read out the result from the sensor?
  10. Hello. I have to adjust the speed (baud), parity bit (if I want), stop bit. For both software alike. I would like to know if anyone has that code in VHDL / VERILOG ? (UART/JTAG)
  11. Hi. I would like to know, if it is possible to modify the sampling frequency, the number of samples of the ADC of the card Nexys 4 DDR ?. I know there are modes of use, but these depend on the registers but do not allow manipulation of these parameters. If you can, I would be grateful if you could tell me how it is possible.
  12. To allow software developers to be able to easily get the computational benefits of FPGAs we created Hastlayer: it turns software written for the .NET platform into an equivalent (VHDL) hardware description. It does this while also handling everything in the background to allow the usage of the resulting hardware in the same way as the original software was run - basically where there was a function call there's still a function call but now it really executes on an FPGA, as logic hardware. Here's a demo video of how it works: And why do I post it here? You can also see
  13. We use Nexys 4 DDR boards for testing our platform. While with most of the Windows host PCs there are no issues, with one of our clients' when the board is plugged in (using the supplied micro USB cable) it shows up as two COM ports under Windows's Device Manager. We suspect this is behind that we can't properly run Xilinx SDK programs on the board, the debugger looses the connection. Is it normal that the board shows up as two COM ports? (When the board is de-attached the ports disappear, so both are surely the single board.) If yes, can this cause issues? If now, how can we begin
  14. Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick
  15. A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: 192.168.1.10 Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use
  16. Hello all, I'm trying to implement Microblaze server on Nexys 4 DDR. Design steps are provide on official website, i follow same procedure as mention on website but while generating Bitstream following error pop up and synthesis failed. please suggest possible errors in design and modification to be done to block diagram. I have attach snap of error message and Block diagram below. PFA, Thanks in Advance Regards, Kumar Khandagle.
  17. Hello ! I'm currently encoutering an issue about how to assign each digit of a number on the seven segment display. For example, if I have the number 1932, how to affect the '2' on the first digit display . The '3' on the second, the '9' on the third, etc... Actually, I have a 4-bit BCD (which functions) and I want to display the decimal number. My output, bcd0, bcd1, bcd2, bcd3 represents the ones, the tens, the hundres and the thousands). I'm decoding each output like that : case bcd0 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_s
  18. Hello ! I'm currently working on a project which consists in designing a digital lock-in amplifier on a FPGA board. For this, I am using a Nexys 4 DDR and an Analog Device's ADC (EVAL AD7984 PMDZ). My first goal is to interface properly the ADC component with the FPGA using a Pmod port. I have some basics knowledge about the use of Vivado so that's why I am asking you about this. I followed the tutorials about "getting started about MicroBlaze" to follow then "using Pmods IP". My question is : When I followed the first tutorial mentionned above, we created a a basic Mi
  19. Hi everybody, I've just received my shiny new Nexys4 DDR board and I've noticed that the DDR2 part is different than that mentioned in the Reference Manual and the schematics which is Micron MT47H64M16HR-25:H. My board (Revision C) has a Mira P2R1GE4KGF - G8E chip. At a cursory read of the data sheets it looks similar to the "original" Micron chip but may not be exactly the same. I'm a newbie here and not experienced with the subtleties of the DDR specifications. My purpose is to learn as much as I can by using the provided examples not to match data sheets Are these chips the s
  20. Hi all, I am using a Nexys 4 DDR board to interface microSD and microSDHC cards using the SPI mode. (For those interested in what the whole thing is all about, click here.) Might it be, that microSD cards are needing current in the range of 10mA (e.g. look at Transcend's 2GB SD card datasheet - link) and microSDHC (SDHC vs SD) are needing 10x of this, e.g. look here at Samsung's 32GB SDHC card: http://www.singerphoto.co.za/SingerPhotographicOnlineDocuments/WebImages/SellSheetPDFs/mesamp64a.pdf How much current is the Nexys 4 DDR SD Card slot able to supply? The first c
  21. Hello, I want to feed video from my smartphone camera to Genesys and want to display the video on the PC. I don't know how to interface. How should I connect my smartphone camera with Genesys board? I also want to do the same thing with Nexys 4 DDR board. Any kind of information will be helpful. Thank You.
  22. Hey all , I am taking a continuous 16 bit serial input from an AFE to nexys 4 ddr board and storing it . Now I have to take this data to pc using usb . I have been searching for this for a long time now (2 weeks to be exact ) but could not find any simple solution . I am using ISE design suite 14.7 VHDL for programming. This is my first fpga project, so please bear my incompetence. Thank you
  23. Hello! I have a Nexys 4 DDR. I'm trying to use an analog sensor like this: https://www.sparkfun.com/products/10264. I want to read data from it with a Nexys 4 DDR but I don't know how to do it. I have tried to read this document: http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf but I didn't understand how to do it. I use Vivado and VHDL. Can someone help me? Thank you!
  24. Have anyone tried successfully to run the advanced I/O demo on nexys DDR ? https://reference.digilentinc.com/nexys4-ddr:userdemo I follow the instruction to create the project, when I run synthesis, it just cannot stop in the procedure.... I got three warnings. WARNING: [Vivado 12-4148] The synthesis checkpoint for IP 'C:/FPGA_project/Tutorial/Nexys4DDR-master/Projects/User_Demo/src/ip/PxlClkGen/PxlClkGen.xci' is not generated and IP is locked, no out-of-context (OOC) run will be created. The synthesis may not be able to complete or could result in incorrect behavior. Ple
  25. Just got a Nexys 4 DDR board for a class and the second I plugged it in, the busy light came on and it hasn't gone off yet and I get a message in Vivado when trying to connect it to the hw_server saying it may be locked by another hw_server?