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Showing results for tags 'nexus 4ddr'.
Hi guys, I've been working on implementation MIG into my project. I have a problem with write data into DDR2 (nexys 4ddr). Actually, it works but, if i want to write data into different address location. The previous one are lost. I can read and write data from the adress but i can't write data into an another addres and read both adress location. some how the previons data are lost. I will be very grateful for any help... process(sig_clk) begin if rising_edge(sig_clk) then case aState is when stInit => if sig_calib_co