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Found 1 result

  1. Hi guys, I've been working on implementation MIG into my project. I have a problem with write data into DDR2 (nexys 4ddr). Actually, it works but, if i want to write data into different address location. The previous one are lost. I can read and write data from the adress but i can't write data into an another addres and read both adress location. some how the previons data are lost. I will be very grateful for any help... process(sig_clk) begin if rising_edge(sig_clk) then case aState is when stInit => if sig_calib_complete = '1' then sig_en <= '0'; sig_wdf_wren <= '0'; sig_wdf_end <= '0'; --LED(15 downto 9) <= (others => '0'); if commnd = CMD_WRITE then aState <= stWriteComd; elsif commnd = CMD_READ then aState <= stReadComd; end if; end if; when stReadComd => sig_en <= '1'; sig_cmd <= CMD_READ; --LED(9) <= '1'; sig_addr(1 downto 0) <= SWI(15 downto 14); aState <= stComdAcep; when stWriteComd => sig_en <= '1'; sig_cmd <= CMD_WRITE; --LED(10) <= '1'; sig_addr(1 downto 0) <= SWI(15 downto 14); aState <= stComdAcep; when stComdAcep => if sig_rdy = '1' then sig_en <= '0'; --LED(12) <= '1'; if commnd = CMD_WRITE then sig_wdf_wren <= '1'; sig_wdf_end <= '0'; sig_wdf_data(12 downto 0) <= "1010101111111"; aState <= stWriteData; elsif commnd = CMD_READ then aState <= stWaitRead; end if; end if; when stWriteData => if sig_wdf_rdy = '1' then sig_wdf_wren <= '1'; sig_wdf_end <= '1'; --LED(13) <= '1'; sig_wdf_data(12 downto 0) <= "1010101010101"; aState <= stWaitAct; end if; when stWaitRead => if sig_rd_data_valid = '1' and sig_rd_data_end = '1' then --LED(14) <= '1'; aState <= stWaitAct; data_out <= sig_rd_data; end if; when stWaitAct => sig_wdf_wren <= '0'; sig_wdf_end <= '0'; --LED(15) <= '1'; if ready = '1' then aState <= stInit; end if; end case; end if; end process;