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Found 4 results

  1. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  2. I'm trying to run the Zybo Z7 Pcam 5C Demo... i'm really new at this, the instructions say: ********************************************************** To generate the project: 1. Open Vivado 2017.4 2. In the tcl console, type "cd [this directory]/proj" and press enter. 3. Type "source ./create_project.tcl" and press enter to generate the block design for the project. To run the demo from SD card: 1. Copy bin/BOOT.bin to the root of your SD card. 2. Set the boot jumper on the Zybo Z7 to SD. 3. Insert the SD card into the Zybo Z7 and power it on. ************************************************** I'm using Vivado 2017.4 and i've copied the board_files to vivado software. After the point 3. (Type "source ./create_project.tcl") I get 7 warnings about some pins... am im doing something wrong here? I'm a newbie. Can you help me out to make the demos work, thanks in advance! ********************************************************************************************************* ## create_root_design "" WARNING: [BD 41-1306] The connection to interface pin /sw_gpio/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO WARNING: [BD 41-1731] Type mismatch between connected pins: /rgb2dvi_0/aRst_n(rst) and /v_axi4s_vid_out_0/locked(undef) WARNING: [BD 41-1306] The connection to interface pin /blur_edge_detect_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl WARNING: [BD 41-1306] The connection to interface pin /color_to_bw_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl WARNING: [BD 41-1306] The connection to interface pin /invert_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/system.bd> Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/ui/bd_c954508f.ui> WARNING: [BD 41-721] Attempt to set value '50000000' on disabled parameter 'C_S_AXI_LITE_FREQ_HZ' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '200000000' on disabled parameter 'kRefClkFreqHz' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '100000000' on disabled parameter 'kRefClkFreqHz' of cell '/video_dynclk' is ignored INFO: [digilentinc.com:ip:axi_dynclk:1.1-17] /video_dynclkFREQ_HZ of 100000000 propagated into CONFIG.kRefClkFreqHz INFO: [digilentinc.com:ip:MIPI_CSI_2_RX:1.0-17] /MIPI_CSI_2_RX_0Verified that video_aclk frequency can handle RxByteClkHS frequency. AXI-Stream bandwidth 600000000 Pix/s >= PPI bandwidth 134400000.0 Pix/s INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 50000000 propagated into CONFIG.C_S_AXI_LITE_FREQ_HZ INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 200000000 propagated into CONFIG.kRefClkFreqHz INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 84000000 propagated onto RxByteClkHS Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/system.bd> VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/synth/system.vhd VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/sim/system.vhd VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/hdl/system_wrapper.vhd make_wrapper: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.461 ; gain = 79.957 # set sdk_dir $origin_dir/sdk # set hw_list [glob -nocomplain $sdk_dir/*hw_platform*] # if {[llength $hw_list] != 0} { # foreach hw_plat $hw_list { # file delete -force $hw_plat # } # } # set sdk_list [glob -nocomplain $sdk_dir/*] # set sdk_list [lsearch -inline -all -not -exact $sdk_list "../sdk/.keep"] # if {[llength $sdk_list] != 0} { # exec xsct -eval "setws -switch ../sdk; importproject ../sdk" # } update_compile_order -fileset sources_1
  3. A recent change to the demonstration Cmod-A7-35 GPIO example (and others) here https://github.com/Digilent/Cmod-A7-35T-GPIO/commit/7bc1448626433ee2c2f493e48bf7b69a76b208b2#diff-a1605eb6dd43eccff08627ccfcfd10fd has removed the create_project.tcl file, which is referenced in your documentation here https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Can you please point me to updated "how to get started" documentation that is valid for vivado 2018.2 and the latest source code repository changes? Thank you
  4. Mark1000

    FPGA getting started

    I'm just starting to learn FPGA and using a Spartan-3E that I inherited from a colleague. I guess you program the FPGA thru the USB connection w code compiled from ISE webpack?? I'm using Windows 10. Is all the necessary sw I need to.."get started" compatible/supported w Windows 10? Thxs.