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Found 18 results

  1. Hello all, After changing PC I want to continue working on NetFPGA-1G-CML board inserted into PCIex16 slot. Board was detected without any problem in my old PC, but my new PC wont detect board as PCI device, its invisible to OS (Linux/Fedora - lspci - device not shown in the list). I tried more motherboards (PCs - like Gigabyte B85M-DS3H and ASUS H81M-R), but without success. Do you know about some constraints/requirements except size and speed of PCIe slot (these requirements are met on tested PCs) of motherboard (or other part of PC), which must be met? I didnt find any information about it in more detail. Thanks for help and any suggestion. My greetings
  2. Hello, We are working on an older system with a Virtex-II pro with rocket I/o and would like to know if the NetFPGA Virtex-II Pro FPGA Development System would be a suitable development board ( it is the same fpga I just need to see if it supports rocket I/o).
  3. Dear all Unfortunately the SUME card micro USB connector was damaged. Although we tried to solder it again, the board is no longer recognized. I would like to replace the micro USB connector but I could not found any reference of the part number. Could you provide me the part number? or any that could fit to the PCB, since there are many type of micro USB PCB connectors. Best Regards
  4. Hello everyone, my tutor at the university asked me to learn how to use an NetFPGA Virtex-II Pro FPGA Development System ( I have no idea where to start so, if anybody can tellme things like if i can use it in a windows (xp, 7, 10) or i need linux. What drivers i need (the idea is to connect it to an pci e port)... A lot of thanx!
  5. Greetings! I'm trying to use NetFPGA-SUME as a NIC and I tried the reference_nic design (in package NetFPGA-SUME-live-release_1.5.0) without changes. However the throughput is quite disappointing: ~2Gbps for RX and ~200Mbps for TX, while the other side of the cable is an Intel 10G NIC. I have spent some time on the source codes and currently I may expect a pair of descriptor rings to improve the performance. I'm not confident that I did everything right, so before stepping forward, I'd like to know: Is the throughput acceptable with the current reference_nic design? If yes, how to improve the throughput and make full use of the bandwidth? If no, is there any special configuration for the reference_nic project? Many thanks in advance! Sam
  6. Hello everyone! I just install a NetFPGA-SUME and I am not sure if it is ok. I followed the getting started guide in, however, something went wrong apparently... In the Section IV: NetFPGA-SUME First Power Up, I followed the steps, but, after turning on the power switch (SW1) it says I should see Power LED (LD10) and DONE LED (LD4) turn on immediately, however I only see the Power LED (LD10) on... in red. The DONE LED is off. In the next step... When I connect USB to my computer I can see a new USB serial device attached [ 13.194737] usb 3-1: FTDI USB Serial Device converter now attached to ttyUSB1 However, when I try to connect, terminal does not respond (I'm using putty to connect /dev/ttyUSB1). Any clue about what is happening? I tried it with the card connect to my server PCI and also stand alone. Also connecting 2x4 and 2x3 PCI express auxiliary power connectors. Thank you in advaned!
  7. xl07

    NetFPGA problem

    HI, does anybody know how to debug NetFPGA, because I find that it spends me 15 minutes to compile the verilog hdl code, once there is a problem, I have to check the verilog hdl source code of NetFPGA in project/reference_switch/src/ manually and recompile the verilog hdl codes.
  8. xl07

    NetFPGA problem

    hi, I have added two registers in project/reference_switch/include/learning_cam_switch.xml as "debug_to_device" and "debug_to_developer", and used the macros "SWITCH_OP_LUT_DEBUG_TO_DEVICE" and "SWITCH_OP_LUT_DEBUG_TO_DEVELOPER" in op_lut_regs.v. But when I use "make" to compile the code, there are 2 errors as following: ERROR:Xst:868 - "../src/learning_cam_switch/op_lut_regs.v" line 168: Index out of range for reg_file_next. ERROR:Xst:868 - "../src/learning_cam_switch/op_lut_regs.v" line 144: Index out of range for reg_file. What is the problem?
  9. Documentation on the NetFPGA-1G-CML (Reference Manual for rev E revised July 16, 2014) says that the FMC connector can support SATA II data rates. I believe that this means 3 Gb/s. Can it also support SATA III (6 Gb/s)?
  10. Hi, I am working on NetFPGA - 1G CML board with Kintex-7 FPGA (xc7k325tffg676). The reference manual for the board specified a set of pin numbers for the 4 Ethernet PHYs on the board, which is shown in the image attached. However, when I synthesized and implemented a small test design which gives inputs to Ethernet Lite IP core to be transmitted across PHY, I got the following error during implementation: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets phy_tx_clk_IBUF] > phy_tx_clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y214 and phy_tx_clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31 On posting a query on Xilinx forums, I was told that pin E13 is not a clock pin, whereas in the manual it is mentioned as phy_tx_clk. I was also directed to this link, which gives the package pin specifications by xilinx. All clock inputs should be given on Clock Capable (CC) pins indicated by SRCC or MRCC. However none of the 4 PHY transmit clocks (B9,D14,J10,E13) are CC pins. I checked the board schematic, but it is the same as the reference manual. I would be grateful to anyone who can guide me on what I should do to overcome this issue. Thanks.
  11. Good evening, We are members of a research team from N.K. University of Athens and ICCS and we are considering NetFPGA-SUME for a research project. The NetFPGA-SUME is equipped with a SAMTEC QTH-DP connector (connected to 8 high-speed serial links). We would like to ask you, if there is a SAMTEC product that directly fits to this connector and has 10Gbits+ SMA pair output ports or another product that we can use with the QTH-DP SAMTEC connector to expand to an FMC with SMA ports (preferably first option). We would like to discuss the available options (I/Os etc) and the pricing of each product, Best regards, Ioannis Patronas
  12. Hey, In V4 version of the doc (and board?), (currently linked on Digilent website), the pin constraints for pcie-rx3_p, pcie-tx3_p, pcie-rx3_n and pcie-tx3_n are wrong, as they are the same as pcie rx/tx port 2 (see first half of page 19 of aforementioned pdf). In V3, (found via Google), I discovered what might be the correct values - it would be nice if someone could confirm them as being right (page 19).
  13. I tested the NetFPGA-1G-CML board with my laptop via a PCMCIA-to-PCIe adapter if it’s running. I use the PE4L-EC060A converter from Bplus company. My test is succesful on very short time. You will consume very short time than setting up NetFPGA within a desktop computer. The materials you need are listed below: SPB087 (ExpressCard 34 to 54 bracket): PE4L-EC060A: V2.1.html My host laptop model is HP-ProBook-6450b and I have to use a 34-to-54 PCMCIA bracket passive device. On the PE4L-EC060A board there are PCB notes layer how to configure the jumpers and switches. My switch configuration and fixed running with NetFPGA-1G-CML board configurations are SW1 PERST# Delay position:1-Disabled and SW2 PCIe card position: 2-3 (x2,4,8,16). (Because NetFPGA-1G-CML board PCIe interface is PCIe x4) No extra power supply needed. It’s very easy. And the jpegs are below too. If you need further assistance regarding this publication you can send an e-mail to [email protected] or go to my blog. Have develop your own open platform network with your mobile host PC and mobile NetFPGA !!! Note: I thank you to my wife Aysegul Kiraba Gol one more again for her trust and belief to my ambition.
  14. Hi all, I am wondering if it is possible to modify the design of the NetFPGA-1G-CML to use SFP (or SFP+) modules instead of 1000base-T. My main interest is in having a board on which it is possible to implement fibre based protocols like GEPON. Are the schematics and layout available for third parties to modify, or is this something Digilent could implement?
  15. What is the target pricing and availability for the new NetFPGA SUME board?
  16. Hi, all I am very interested and want to know (before I buy and start using netFPGA-1G-CML) one important thing about HW used with this card. Do I need special hardware except PCIe slot to use netFPGA? I want to use it on classical desktop PC with PCIe X16 slot. Now I dont know if this card needs special kind of CPU or other HW component. Thank you for help. I am waiting for your answers, because I didnt find anything about this.
  17. Hi, I've just received two of these, both marked on the silk screen as Rev F. I was looking at the Rev E.0 schematic which seems to show the DDR3 device, IC23, as a MT41K512M8RH (a 1.35v DDR3L device) being fed from IC36, a 1.5v power supply. I checked my board and the memory IC23 is marked "D9QBJ" which according to the Micron website agrees with the part shown on the schematic, is an "RH" 1.35v device. I also checked the voltage test point next to IC36 and that rail is definitely 1.5v. I think there is a problem that the supply to this memory is above the above the maximum operating voltage in table 21 of the Micron datasheet. I would appreciate it if someone from Digilent could comment please. regards, Jason
  18. What will I have including reference designs and accessories in the NetFPGA 1G CML kit?