Search the Community

Showing results for tags 'modelsim'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 1 result

  1. Hi, I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'. In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition, The interface of BRAM is blk_mem_gen_0 uut( .clka(clka), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clkb), .web(web), .dinb(), .addrb(addrb), .doutb(doutb) ); for address and data, #0 wea=1; web=0; addra=0; dina=0; #10000 addra=1; dina=2; #100 addrb=0; #1000 addrb=1; #30000 $stop; In simulate wave,dout is always x. What makes it? Regards, Sophia