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Found 10 results

  1. Objective: Transmission of Non-MIPI camera sensor data (i.e. any monochrome sensor) using MIPI CSI-2 TX Controller Ip core from on one Arty7 Board to another Arty7 board as MIPI CSI-Rx system or any MIPI Receiver based Video processor. IP core Application: The Xilinx MIPI CSI-2 TX Controller implements camera sensor transmitter interface over MIPI D-PHY Interface. It can be used to bridge between non-MIPI camera sensors to MIPI based video processor. This Core provides combination of MIPI CSI-2 transmit controller and D-PHY interface. System Overview as per our understandi
  2. Hi all, I download the "ZedBoard-FMC-Pcam-Adapter-Dual-Camera-2018.2-1" and open it on vivado 2018. There are four MIPI D-PHY (A,B,C,D). In #A, we have a RxByteClk = 84MHz, which can be derived from total data rate =1344Mbps. However, when i check the configuration of #B,#C,#D, all of them have RxByteClk = 25MHz. Can I know how the difference or how the 25MHz be derived? Thanks. BR
  3. I'm trying to use Pcam FMC with a ZCU102. I've looked through this post so I know there may be a way forward by editing the netlist using post synthesis constraining. Because the I2C switch select lines are grounded on the ZCU102, I can only communicate with CAMA so going to use this as a one camera interface. I've also verified the IO requirements and other architecture requirements. So far, I don't see anything stopping me from using to interface with camera A with a ZCU102. However, I want to use the MIPI D-PHY Xilinx IP but need help with the configuration. Looking through the timing
  4. Hello, I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project. I want to replace the Digilent MIPI_D_PHY_RX with the Xilinx MIPI D-DPHY. My issue is, that the Xilinx MIPI D-PHY does not output any AXI-Stream signals and that I see permanent 'Start-of-Transmission (SoT) Error' (errsoths = '1') reported on the output port of the Xilinx MIPI D-PHY. This error occurs, according to the Xilinx MIPI D-PHY datasheet, when the HS_SETTLE parameter is not matching. The standard HS_SETTLE pa
  5. Sduru

    AXI4 and Vivado ILA

    Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to I
  6. Sduru

    MIPI D-PHY and CSI-2

    Hi everyone, I am dealing with MIPI CSI-2 RX and D-PHY RX IPs which are open source IPs by Digilent. Where is the latest versions of those IPs? Is there new versions of those which are compatible with Vivado 2018.3? Many thanks...
  7. Hi all, I'm trying to connect a MIPI camera (Rpi camera v2) to the Digilent Nexys-4 DDR board through the JXADC connector. Since these pins are routed for differential signaling, the JXADC connector seemed the best option for this, but I soon ran into a couple of problems though: - the JXADC pins are not connected to any clock input pins on the Artix-7, so I get placement errors when trying to connect the MIPI clock lane to these pins. I found out there is only 1 P-version clock input pin available on all the PMODs, namely JB10 (which connects to H16 on the Artix-7), so I trie
  8. Hi all, I have a Zybo and have been using it successfully for a variety of HDMI / VGA video projects. I'd like to have a go at interfacing a Raspberry Pi V2 camera. I understand that I need to implement a MIPI CSI-2 receiver in VHDL and I have a reasonable idea of how to proceed. This may take a bit of effort, but that's part of the fun! However, what I'm not sure about is whether I can specify the appropriate 1.2v IO Standard that's required on the Zybo board via the high speed PMOD ports? Or, will I need to buy one of the newer Zybo-Z7 boards? I realise that the newe
  9. tl;dr: custom design for MIPI bridge to an Arty with no transceivers, besides coming to my senses, what's the best way to tackle this? --------------------------------------------- Summer uni project. My task is getting image data from a MIPI camera sensor (OV5467; the Raspberry Pi camera) into an Arty board. No high speed transceiver pins on it, and no native support for interfacing to MIPI. Just the HP IOs on the middle Pmods. Our fall-back is to just take image data in via the Raspberry Pi and squirt that via UART or SPI into the Arty to demonstrate parallelized image p
  10. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter i