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Found 6 results

  1. Sduru

    AXI4 and Vivado ILA

    Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to ILA directly? If it is possible only with AXI interface, so I will deeply study the AXI4 referance manuals. Many thanks...
  2. Sduru

    MIPI D-PHY and CSI-2

    Hi everyone, I am dealing with MIPI CSI-2 RX and D-PHY RX IPs which are open source IPs by Digilent. Where is the latest versions of those IPs? Is there new versions of those which are compatible with Vivado 2018.3? Many thanks...
  3. Hi all, I'm trying to connect a MIPI camera (Rpi camera v2) to the Digilent Nexys-4 DDR board through the JXADC connector. Since these pins are routed for differential signaling, the JXADC connector seemed the best option for this, but I soon ran into a couple of problems though: - the JXADC pins are not connected to any clock input pins on the Artix-7, so I get placement errors when trying to connect the MIPI clock lane to these pins. I found out there is only 1 P-version clock input pin available on all the PMODs, namely JB10 (which connects to H16 on the Artix-7), so I tried using JB10 & JB3 (N-version clock input) for the MIPI clock lane pair. I realize this pair will not be optimally routed for differential signaling, but it's the only option I can find. - the JXADC pins all connect to bank 15 on the Artix-7, which is the same bank as the DIP switches and LEDs. This gives errors when trying to use LVDS_25 on the JXADC pins, while also using the DIPs and/or LEDs, since they are LVCMOS33 and you can't have 3.3V as well as 2.5V on the same bank. Then I've seen a couple of posts on this forum from zygot, stating there are a lot of problems with this, which got me a little spooked. I didn't understand ALL of what is said on his posts, so the question I would like to ask here is: Is it at all possible to connect a camera with MIPI CSI-2 interface (2 data lanes, 1 clock lane) to the Digilent Nexys-4 DDR board or shouldn't I bother trying to get it work? I already constructed a small PCB following to the Xilinx XAPP 894 application note to make a D-PHY compatible connection to the Artix-7 pins, but now I'm afraid the board itself won't allow it. I've already spent some time on this, so I just want to make sure I'm not wasting any more time if it is not at all possible. Thanks in advance for your expertise. Koen
  4. Hi all, I have a Zybo and have been using it successfully for a variety of HDMI / VGA video projects. I'd like to have a go at interfacing a Raspberry Pi V2 camera. I understand that I need to implement a MIPI CSI-2 receiver in VHDL and I have a reasonable idea of how to proceed. This may take a bit of effort, but that's part of the fun! However, what I'm not sure about is whether I can specify the appropriate 1.2v IO Standard that's required on the Zybo board via the high speed PMOD ports? Or, will I need to buy one of the newer Zybo-Z7 boards? I realise that the newer Zybo-Z7 boards have a 2 lane MIPI connector (which is very convenient), so I'm assuming that the connected Zynq pins can run in the appropriate 1.2v differential IO Standard. But for this to work does the newer Zybo-Z7 have a specific 1.2v VCC supply to facilitate this? (that perhaps the Zybo doesn't have) I will probably upgrade to the newer board anyway, but would like to understand if this is possible on the older Zybo. Many thanks!
  5. tl;dr: custom design for MIPI bridge to an Arty with no transceivers, besides coming to my senses, what's the best way to tackle this? --------------------------------------------- Summer uni project. My task is getting image data from a MIPI camera sensor (OV5467; the Raspberry Pi camera) into an Arty board. No high speed transceiver pins on it, and no native support for interfacing to MIPI. Just the HP IOs on the middle Pmods. Our fall-back is to just take image data in via the Raspberry Pi and squirt that via UART or SPI into the Arty to demonstrate parallelized image processing. However, the disparity between input-output rates and the rate at which our configured logic can process the image is so significant, we feel it's a waste of an FPGA. I have perused XAPP894, IOSelect resources for Artix-7 devices, and the IP catalogs in Vivado for CSI-2 Rx/Tx IP, etc. I think we can get the IP on a uni license. A faculty member helping us is keen to fabricate a custom PCB for bridging MIPI to other standards (like the LVDS_25 on the Arty). If I can bring him a viable design for this bridge he will get it fabricated. I think he might even take care of the PCB design as long as I can bring him a circuit schematic that will work. --------------------------------------------- My questions to y'all 1) should I go with a passive RC network (p10 of XAPP894) for D-PHY compliance or use a vendor-bought bridging IC? 1a) if an RC network, then how precise/accurate/tolerant do my passive component values need to be? 2) should I be simulating this bridge for signal integrity, say with Ibis in Altium, before submitting the design? (I have zero exposure to Altium, let alone simulating for signal integrity) 3) should we just consider switching to a Zedboard (there are a few floating around upstairs) if it has MIPI D-PHY compliant ports? Or is the challenge of a custom bridge worth it? (I am a virgin with this stuff, very little experience) --------------------------------------------- any other advice, comments, recommendations, jibes or anecdotes are more than welcome Thank you.
  6. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at http://archive.eetasia.com/www.eetasia.com/ART_8800715969_499489_TA_a466fca2_3.HTM there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)" "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first." Using VHDL and Vivado, how do I create logic to successfully read data from this sensor? I have the following code written (with notes/questions) but I'm pretty sure its wrong. It was put together based on my limited understanding and reading various other source code that perform similarly: http://pastebin.com/FGvChHis I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value. If it is 1, increment the delay value. This way the delay should always be within +/- 1 of the ideal value. I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute). This is probably due to random chance. Really need help on this one!