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Found 4 results

  1. Hello everyone, I am trying to control the output of the LEDs of my board with MIO, as shown in this example. The thing is that looking at the schematic of my Cora Z7 board, the LEDs do not appear in the MIO bank. Is it at all posssible that the board does not offer the possibility to configure MIO rgb leds as outputs? Thank you and have a nice day.
  2. Trillian

    arty7 / pynq-z1 LED MIO

    Hi, I'm having exactly the same problem that this person had: http://www.zedboard.org/content/zedboard-pins-banks-and-mio I'm trying to find the MIO Pin Numbers for the LEDs on the PYNQ-Z1 / ArtyZ7 board. The solution for the above user seemed to be checking out some table in the HW Guide. My board doesnt even seem to have a HW guide. Ich checked the following resopurces: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start https://reference.digilentinc.com/_media/reference/programmable-logic/pynq-z1/pynq-rm.pdf So where can I find the complete MIO? thanks! T
  3. yui202

    Short circuiting MDIO

    Hi there, I'm working on a project (using the Zybo development board) where I am attempting to drive a bidirectional bus. Due to the speed of this bus I have had to connect the pins on the development module to the high speed differential PMOD connectors on the board. These headers (JB, JC, JD) lack the series termination resistors that the lower speed PMODs have on the board to protect against short circuit currents. What I am wondering is does this present any immediate danger to my development board if I make a mistake in my code and there is a situation where the chip I am communicating with attempts to pull a data line low whilst I am attempting to drive it high on the FPGA side. Is there any way I can check my board for damage, because after debugging today I seemed to get some weird behaviour while testing my code that has led me to believe that it is a hardware related fault. As a sort of part 2 to this question; Is there a better way to check my VHDL source code for errors before synthesis than what I am currently doing which is simulating responses from the bus directly writing a VHDL testbench for the scenarios I might encounter. I have looked everywhere for how I can automate test bench generation but there doesn't appear to be much software out there for this purpose. I'm sure there must be an answer to this somewhere, given that this seems like a common scenario (building interfaces to common communication standards). Surely there must be a tool that is well established for automating the generation of testbench code for this scenario (simulating designs based on a particular interface specification) or perhaps there are tools which can make the process faster. If anyone can help me out here by answering any of these questions that would help me a lot. Thanks.
  4. Hello I installed the newest Vivado 2016.2 and the newest Zybo board files from git repo. Any attemp to build the project ends with multiple Warnings during the place phase, saying that some Mio ports have more than one voltage standard. And the placement never ends. It happens even when I try the simplest BD with Zyng core and two AXI_GPIOs for leds and buttons. any idea?