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Found 4 results

  1. Hello all, I've been working on an audio looping project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also involved setting up a clock backbone route in my constraint file. Instantiation: I've been instantiating my MIG with inputs set to 0 (except clocks) and outputs left open, just trying to get that init_calib_complete signal to go high. clk1 : clk_wiz_0 port map ( -- Clock out ports clk_out1 => clk_ref, -- Status and control signals resetn => reset_n, -- Clock in ports clk_in1 => sys_clk_ibufg); u_mig_7 : mig_7 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, init_calib_complete => init_calib_complete, ddr3_odt => ddr3_odt, -- Application interface ports app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => (others => '0'), app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => open, app_rd_data_valid => open, app_rdy => open, app_wdf_rdy => open, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => open, app_ref_ack => open, app_zq_ack => open, ui_clk => open, ui_clk_sync_rst => open, -- System Clock Ports sys_clk_i => sys_clk_ibufg, -- Reference Clock Ports clk_ref_i => clk_ref, sys_rst => reset_n ); Constraints: I have one user constraint file bringing in the 100MHz clock from the board as well as buttons, switches, leds, and the audio codec signals for debugging and other functionality. It's attached to this post. MIG setup wizard settings: If anyone has experience with using this MIG or any clocking expertise, please let me know. I've been banging my head against this just hoping for a calibration, and I would really appreciate your help. Thank you!
  2. I went through the process of running MIG7 (Vivado 18.3) to generate a DDR3 controller for the Arty A7-100. I copied the digilent board files into the Vivado 18.3 board_files directory and chose arty-a7-100 when opening my project. When MIG7 starts, the first thing it wants is clock period. That's where I'm having the problem. MIG7 allows numbers between 2500 and 3300ps. But with my board, MIG7 won't allow any period less than 3225ps. That's a very narrow range of frequencies! I need to consider my FPGA general system clock speed in connection with making a high-speed UART for PC communication. Between 3225ps (310.7Mhz) and 3300ps (303Mhz), there are no useful frequencies I can find in common with baud rates that are multiples of 1,000,000. If the tool allowed 3333ps, I'd end up with an FPGA clock of 150Mhz (with 2:1 ratio). I could make that work easily. After looking at the "stub" Verilog file and reading in UG586, I see that sys_clk_i is a user input. Could I not feed 300Mhz in there? I don't care that memory would be a tiny amount slower. Would the DDR controller not work? Is there any reason the tool could not directly allow a slower clock specification? Thanks for all your help. Let me know if any file I have would be helpful to you on this. Allan
  3. Hello! I cannot debug the DDR3 outputs/inputs. I get the following error message. Bus interface connection '/mig_7series_0_DDR3' is connected to interface '/mig_7series_0/DDR3' with VLNV xilinx.com:interface:ddrx:1.0, which is not debug-able by System ILA IP. HDL attribute 'DEBUG' will not be set to this bus interface connection. Could anybody help me with this? I am going to check if my 640x480 picture is saved in the ddr3 but I have to use the ILA which does not work atm. regards, John
  4. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture of the the system I obtained at the end but this website would not let me. Any way, my system matches exactly the one in the tutorial. The validation passed, synthesis also passed ( although it gave me the same error the tutorial asked me to ignore, which I did). However, before running implementation I ran a "Report Timing Summary" from the Synthesized Design sub-menu, It gave me the several errors related to the oserdes_clk... To make sure these errors were not caused by something I may have entered wrong while creating the project, I decided to re-do the project starting from a blank slate, but the results were exactly the same in the new project. I tried to paste here an image with the errors but this website would not let me .... Anyway, the errors were Inter-clock paths / oserdes_clk to oserdes_clk / Hold -0.246ns (10 occurrences) Below is one of the Interclock paths that had the Hold timing error From: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK To: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST I think the error is due to a lack of one or more timing constraints. I suspect there might be an error with the board files associated to the Nexys-Video board, specifically related to the MIG7 and the DDR . I do not have enough knowledge of the system to be able to make the constraints myself. How could I solve these timing errors? Thanks