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Showing results for tags 'mig7'.
Hello all, I've been working on an audio looping project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also
I went through the process of running MIG7 (Vivado 18.3) to generate a DDR3 controller for the Arty A7-100. I copied the digilent board files into the Vivado 18.3 board_files directory and chose arty-a7-100 when opening my project. When MIG7 starts, the first thing it wants is clock period. That's where I'm having the problem. MIG7 allows numbers between 2500 and 3300ps. But with my board, MIG7 won't allow any period less than 3225ps. That's a very narrow range of frequencies! I need to consider my FPGA general system clock speed in connection with making a high-speed UART for
Hello! I cannot debug the DDR3 outputs/inputs. I get the following error message. Bus interface connection '/mig_7series_0_DDR3' is connected to interface '/mig_7series_0/DDR3' with VLNV xilinx.com:interface:ddrx:1.0, which is not debug-able by System ILA IP. HDL attribute 'DEBUG' will not be set to this bus interface connection. Could anybody help me with this? I am going to check if my 640x480 picture is saved in the ddr3 but I have to use the ILA which does not work atm. regards, John
I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture