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Found 7 results

  1. davec

    Problems with MIG_7

    Has anyone had problems trying to use MIG_7 in their block diagrams in Vivado? I had a design that was working under version 2015.3, then something went wrong. Whenever I try to select that IP block in my diagram, vivado hangs trying to open it. I tried deleting it from my design and bring in a new mig_7series block from my list of board components and it hangs as well. I brought my design over onto a different Win7 computer and did a fresh install of a newer vivado 2017.3 with the latest board files with the exact same result- when I try to bring in the mig block, vivado hangs forever.
  2. When I ported the w11 CPU design from Nexys4 to Nexys A7 I didn't use the SRAM to DDR component but wrote my own interface layer which queues writes and includes a 'last row buffer', see sramif_mig_nexys4d and sramif2migui_core. I had a look at the Nexys 4 DDR Xilinx MIG Project and was a bit astonished to see that the SYS_CLK was 200 MHz <TimePeriod>3333</TimePeriod> <PHYRatio>2:1</PHYRatio> <InputClkFreq>200.02</InputClkFreq> I really wonder why Digilent recommends this. It is possible to use 100 MHz, to use the board cl
  3. Hi, I am experiencing an issue with the mig 7 series interface for Arty S7-50 on Vivado 2017.2. I downloaded the board files from the and copied them in C:\Xilinx\Vivado\2017.2\data\boards\board_files\. Adding the DDR3 SDRAM from the board tab or a MIG interface using add IP and trying to customize it always result in the error below. Has anyone experienced this? Thanks.
  4. Hi guys, I've been working on implementation MIG into my project. I have a problem with write data into DDR2 (nexys 4ddr). Actually, it works but, if i want to write data into different address location. The previous one are lost. I can read and write data from the adress but i can't write data into an another addres and read both adress location. some how the previons data are lost. I will be very grateful for any help... process(sig_clk) begin if rising_edge(sig_clk) then case aState is when stInit => if sig_calib_co
  5. Hey there, I currently try to use the ddr memory on the arty board. Therefore you provide some files (I assume to configure the ddr within the MIG-7 IP) on your homepage. When I try to customize the MIG IP in my project (which is configured to the arty board, with the provided board files - Revision C - on your homepage), I try to load the provided .prj and .ucf file and the customization of the MIG-IP crashes. I googled the error and the xilinx homepage tells me the reason is that the artix-fpga on the arty board is not supported for MIG usage. Can anybody help me with this issue or maybe pro
  6. Pedro

    Nexys4 DDR & MIG

    Hi, I am trying to understand how to generate a MIG based memory controller in the Nexys4 DDR board, I am reading the UG586 (Memory Interface Solutions), but I am not sure about the system clock and the reference clock. Should I mark them as "no buffer" in the GUI and connect them in the top level source with a 200MHz clock to both of them? Thanks in advance for your help best regards, Pedro
  7. AlbertoEnablia


    I would ask you if it is possible to have the Vivado or ISE Core Generator Project of a typical MIG configuration for DDR3 interface of your NETFPGA-1G-CML board. Thanks in advance.