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Found 89 results

  1. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  2. Just like this post here, my out of the box example's ethernet is not working. In trying to follow the guide. Changed link speed to 100 as it said. The echo server isn't working, keeps saying the link is up then down, and my computer keeps connecting then disconnecting. All within about a second, so I don't have nearly enough time to see if anything is working even when it is "connected". So then I tried the peripheral test project, and I got an "AxiEthernet: Rx fifo over run" on the "AxiEthernetSgDmaIntrExample". So I increased the rx buffer in the IP re-customization to the max 32KB, no luck. I added some outputs to try and debug it, added the Axi dma bd ring checks to the tx & rx buffers, both pass. The example also errors with "Length mismatch" as it is not receiving everything it sent. When I do a debug launch I don't get the fifo over run, so either a coincidence or something is acting up. I also have it printing out the lengths of the rx/tx, tx is 1014, rx varies as low as 60 and as high as 216 from what I've seen so far. All the other tests (ethernet dma, timer ctr, timer interrupt, axi intc) passed. When I try unplugging the ethernet cable it hangs on waiting for the bytes to come back which I suppose makes sense. I'll attach my xsa. I've been setting the programming mode to JTAG so as far as I know the builtin example is still sitting there on the QSPI for if I need it. I couldn't get the code to build with 2020.1 even after upgrading everything, so I can't try that as a fix. EDIT: managed to get the echo working by polling the BMSR register and waiting for the negotiation complete bit to be set design_1_wrapper.xsa
  3. I have an old Spartan 3E Starter Kit and I need to develop an embbeded system. Such system targets an acceleration for a specific computation process. To do so, I will employ MicroBlaze for the management process connected to a vhdl block which is the piece of hardware that will perform the acceleration itself according to Figure 1. Figure 1 - basic scheme for my acceleration process The design is being done in XPS (the hardware) and in Eclipse SDK (the software). In the C software I will employ a send function which will pass to the acceleration VHDL block. The process will be performed and a receive function will gather the result to be presented, e.g., in the LCD. It is my intention to develop my vhdl block will be specified via "Create and Import Peripheral Wizard". My problem: I don´t know how can I specify my VHDL acceleration block net ports, i.e., if they are external, or how type I can classify them. I have examples of how to connect actual peripherals, such as dip switches, leds, LCD. In all these examples, they are classified as "Make External" ones. I go to the .ucf file, insert the respective information, and everything goes fine. But, in my case, as show in Figure 1, my connection to the MicroBlaze is internal, inside the FPGA. Trying to solve this, I am using a 4-bit integer multiplier as my "acceleration block". This MWE block receives the a and b operands, each one of them with four bits, performs a basic multiplication, and gives an 8-bit result. Any help will be appreciated.
  4. Hi, I am playing with the nexys video user demo. I have changed the bitstream to display an overlay (BITC) instead of mouse pointer, and I can bake the bootloader into the bitstream and write it to the flash. I now want to change the microblaze software, which appears to be at flash address 0xa00000. What format image do I write there? Is it the ascii SREC file? James
  5. dfdias


    Hi was trying to interface the accelerometer available on the nexys 4 board. But i was not getting any data. Then I mapped the output pins to the JA PMOD header so I could probe them Using an logic analyzer I saw that the sclk and Chip_select were working but the MOSI signal is full of zeroes. I connected an 50MHz clk coming from the clock wizard, and then connected it to the ext_spi_clk and used an scale of 16 so the clk is about 3.16MHz Below is the Block_Design helloworld.c Below is the data I acquired using saleae logic analyzer: I submitted the C files containing the main (helloworld.c) wich is a almost linear copy of the polled example; The accelmacros file has some values with the commands and register addressees of the SPI slave. Do you have any hint of what I am missing? Thanks in advance. accelmacros.h
  6. Billel

    Microblaze sleep mode

    Hello How can I put the Microblaze in standby mode and reduce its power consumption? regards,
  7. Hello, I'm a student and currently working on my final project including Basys 3 board and wifi pmod. I'm trying to get started working with the module to understand how it works. This is my first project working with Pmods. I've been using the Getting Started with Digilent Pmod IPs tutorials. I added the newest Vivado library including the PmodWifi IP and I bulit a block design with the MicroBlaze and other GPIO IPs. I followed the instructions of the tutorials and got to the part of validating the design, there I got a warning saying few of the wifi pmod pin are not connected. I've got a few other warnings and errors so I really don't understand what went wrong. If anyone know what the issue is and can help me, that would be awesome! Also I'm looking for an example project for wifi pmod using Microblaze to learn from. I'm attaching some screenshots of my project. thanks, Netanel.
  8. I am starting with working design for the CMOD S7 where I program the device through SDK and all functionality works as intended. Now where I am falling short is getting the program to run out of the SPI Flash. I have been following the "How To Store Your SDK Project in SPI Flash" guide from Digilent in order to put a Microblaze design into SPI Flash on the CMOD S7 located at the link here: There is a recommended offset of 0x00300000 for the CMOD A7 - My question is what is the recommended offset for CMOS S7? I tried both 0x00000000 and 0x0030000 and could not get the design to work. Kind Regards, James
  9. Dear Support, I am trying to implement a Microblaze in the Arty S7 with 50T FPGA board revision E. (yes Rev E not B). I instantiate GPIOs, Switches, LEDs, pushbuttons, UART and SPI at J7. I want to write c code to control the LEDs and talk to an SPI device. Attached is my implementation in picture format. The design verifies, synthesizes, and implements, but I get timing is negative. ISSUES 1. I am not sure how the GPIOs route from the block diagram to constraint file. I downloaded the constraint file, and uncomment the clock, and GPIO switches, etc...However, in the block diagram net names do not match the constraint file. I don't know how to map them In the case of the clock, I matched the Net CLK_12MHz in the block diagram to the constraint file, but for the GPIO, and others I am not sure I am doing this correctly. 2. Timing fails no matter if I change the CLOCK_OUT from 100MHz, 96MHz, 80MHz. Timing fails. HOW TO IMPLEMENT THE CONSTRAINT FILE TO BLOCK DIAGRAM...They should match no? Please advise how to fix timing, and how to map constraint file. I am sure I am not doing this right. I have watched numerous videos on implementation, and every implementation passes but they don't show how they setup other stuff. ## Clock Signals set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports CLK_12MHz]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports CLK_12MHz]; ## Switches set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0] set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2] set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3] ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Buttons set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1] set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2] set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3] ## USB-UART Interface set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in ## ChipKit SPI Header ## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time. set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck # Misc. ChipKit Ports #set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports RESET_N]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] # SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] Arty-S7-50-Rev-E-Master.xdc
  10. Hi I am new to microblaze. I have to design an efficient ALU using microblaze in Nexys 4 Anyone can guide through me the procedure ( I know the general guide line) and refer any document to do it Regards Uzmeed
  11. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin // then count value flip over to zero, then make led on or off led <= ~led; // in the always loop, it needs to use registers end count <= count +1; // add the count value until it flips over to zero end else begin // if there is no key to be pressed, init the led to off state; led <=0; count <=1; end endmodule and I included this module in IP design. and the errors were like below. before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed' I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? Thank you for your kind answers, ...
  12. Hi all, This is a quick and dirty howto. This howto describes how to use I2C modules (onboard and through PMOD connector) under embedded Linux. I've chosen to build my own Linux distro based on Linux kernel source for MicroBlaze softcore and busybox project for the init RAM DISK. My board is the Nexys4 DDR board. If you respect the following requirements for the HW design compatible with Linux, you can use Petalinux too. HW Vivado requirements (according to Xilinx UG1144) design to boot Linux: MicroBlaze with MMU support by selecting either Linux with MMU or Low-end Linux with MMU configuration template in the MicroBlaze configuration wizard. External memory controller with at least 32 MB of memory. Dual channel timer with interrupt connected. UART with interrupt connected. Ethernet with interrupt connected. Note that all peripherals you use must be interrupt capable. For the UART peripheral, if you have not enabled interrupts, you have no Linux console outputs. For the Nexys4 DDR, you can follow this online tutorial: At this stage, for the Nexys4 DDR board, you can add the onboard i2C temperature sensor (ADT7420) that uses the AXI IIC IP block. I've added a second external temperature sensor (PMOD TMP3) connected to PMOD JA pins of the Nexys4 DDR board. I've chosen to connect SCL TMP3 pin to JA1 PMOD JA pin (C17 FPGA pin) and SDA MP3 pin to JA2 PMOD JA pin (D18 FPGA pin). You connect GND and 3V3 pins from PMOD JA connector to corresponding TMP3 pins. You have finally 4 pins to connect. You obtain the Vivado design shown below. Notice that both AXI IIC IP blocks have interrupts connected for Linux compatibility. For the TMP3 sensor, I have an external port named temp3_sensor. I've created a XDC file containing: set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { tmp3_sensor_scl_io }]; set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { tmp3_sensor_sda_io }]; You can see that: tmp3_sensor_scl_io signal is for SCL I2C signal. tmp3_sensor_sda_io signal is for SDA I2C signal Please respect notation: xxx external I2C port gives xxx_scl_io and xxx_sda_io signal names in the XDC file. Generate .bit file. Launch Vivado SDK tool, install the device tree plugin and generate Device Tree files. You can follow this link: Copy the generated pl.dtsi file (under project_1/project_1.sdk/device_tree_bsp_0/ directory) into arch/microblaze/boot/dts/ Linux directory. Use the generated system-top.dts file (under project_1/project_1.sdk/device_tree_bsp_0/ directory) to create the xilinx.dts file into arch/microblaze/boot/dts/ Linux directory. Be carefull with stdout options in the xilinx.dts file if you want Linux output enabled. Mine is: /dts-v1/; /include/ "pl.dtsi" / { chosen { bootargs = "console=ttyUL0,9600"; linux,stdout-path = &axi_uartlite_0; stdout-path = &axi_uartlite_0; }; aliases { ethernet0 = &axi_ethernetlite_0; serial0 = &axi_uartlite_0; i2c0 = &axi_iic_0; i2c1 = &axi_iic_1; }; memory { device_type = "memory"; reg = <0x80000000 0x8000000>; }; }; &axi_ethernetlite_0 { local-mac-address = [00 0a 35 00 00 00]; }; Generate your init RAM Disk for root File sytem. I suppose that you can do this. Generate your Linux kernel. I suppose that you can do this: $ make ARCH=microblaze CROSS_COMPILE=microblazeel-xilinx-linux-gnu- simpleImage.xilinx -j 4 Program the FPGA device and download the simpleImage.xilinx file (kernel + init RAM Disk) under arch/microblaze/boot directory into RAM with the JTAG interface and finally execute. That's all folks! Ramdisk addr 0x00000000, Compiled-in FDT at c03ad4f8 Linux version 4.14.0-00493-gb68293ad2c93-dirty ([email protected]) (gcc version 8 setup_cpuinfo: initialising setup_cpuinfo: Using full CPU PVR support wt_msr_noirq setup_memory: max_mapnr: 0x8000 setup_memory: min_low_pfn: 0x80000 setup_memory: max_low_pfn: 0x88000 setup_memory: max_pfn: 0x88000 Zone ranges: DMA [mem 0x0000000080000000-0x0000000087ffffff] Normal empty Movable zone start for each node Early memory node ranges node 0: [mem 0x0000000080000000-0x0000000087ffffff] Initmem setup node 0 [mem 0x0000000080000000-0x0000000087ffffff] On node 0 totalpages: 32768 free_area_init_node: node 0, pgdat c0525af4, node_mem_map c07a2000 DMA zone: 256 pages used for memmap DMA zone: 0 pages reserved DMA zone: 32768 pages, LIFO batch:7 pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 pcpu-alloc: [0] 0 Built 1 zonelists, mobility grouping on. Total pages: 32512 Kernel command line: console=ttyUL0,9600 PID hash table entries: 512 (order: -1, 2048 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 121948K/131072K available (3765K kernel code, 121K rwdata, 1312K rodata) Kernel virtual memory layout: * 0xffffe000..0xfffff000 : fixmap * 0xffffe000..0xffffe000 : early ioremap * 0xf0000000..0xffffe000 : vmalloc & ioremap NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 irq-xilinx: /amba_pl/[email protected]: num_irq=5, edge=0x6 /amba_pl/[email protected]: irq=1 clocksource: xilinx_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_is xilinx_timer_shutdown xilinx_timer_set_periodic sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns Calibrating delay loop... 49.15 BogoMIPS (lpj=245760) pid_max: default: 4096 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) random: get_random_u32 called from bucket_table_alloc+0x2e4/0x35c with crng_ini0 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191s NET: Registered protocol family 16 clocksource: Switched to clocksource xilinx_clocksource NET: Registered protocol family 2 TCP established hash table entries: 1024 (order: 0, 4096 bytes) TCP bind hash table entries: 1024 (order: 2, 20480 bytes) TCP: Hash tables configured (established 1024 bind 1024) UDP hash table entries: 128 (order: 0, 6144 bytes) UDP-Lite hash table entries: 128 (order: 0, 6144 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. random: fast init done Skipping unavailable RESET gpio -2 (reset) workingset: timestamp_bits=30 max_order=15 bucket_order=0 io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) io scheduler mq-deadline registered io scheduler kyber registered Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 40600000.serial: ttyUL0 at MMIO 0x40600000 (irq = 5, base_baud = 0) is a uartlie console [ttyUL0] enabled brd: module loaded libphy: Fixed MDIO Bus: probed xilinx_emaclite 40e00000.ethernet: Device Tree Probing xilinx_emaclite 40e00000.ethernet: Failed to register mdio bus. xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00 xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF02 i2c /dev entries driver NET: Registered protocol family 17 Freeing unused kernel memory: 2296K This architecture does not have kernel memory protection. Hostname : nexys4ddr Kernel release : Linux 4.14.0-00493-gb68293ad2c93-dirty Kernel version : #120 Thu Dec 6 16:51:57 CET 2018 Please press Enter to activate this console. nexys4ddr:/# For the first I2C sensor (onboard ADT7420 sensor of the Nexys4 DDR board), we must use the /dev/i2c/0 (or /dev/i2c/i2c-0) character driver file (Major=89 minor=0). For the second I2C sensor (external TCN75A PMOD TMP3 sensor), we must use the /dev/i2c/1 (or /dev/i2c/i2c-1) character driver file (Major=89 minor=1). nexys4ddr:/# i2cdetect -y 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- 4b -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- nexys4ddr:/# i2cdetect -y 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- 48 -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- You can now use the Linux API for reading the I2C sensors... Pat.
  13. ozden.erdinc

    Vivado AXI QUAD SPI

    Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.
  14. I am following the steps outlined in I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor. The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest. [DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user assigned specific location constraint (LOC). I have attached the full error and block design. ---- I wish to add a couple of comments regarding Vivado. In my installation on two different computers; in step 5.2 when defining the Top Module, the 5.2 recipe does not work for me on these two Windows installations. However, if one exits Vivado and restarts Vivado, the top module magically appears. However, if one starts Vivado from its desktop icon, Vivado get confused as to what is its project name. If one starts Vivado at this point from the file name in the project directory (ProjectName.xpr) the problem goes away. (See attachment VivadoProjName.JPG, project name is GettingStarted_3) GettingStarted_error.txt
  15. Hi @jpeyron, Hi all, I want to read data from IOmodule, then send this data to a PmodDA3 module using Microblaze. What is the right procedure to read data from IOmodule ? Kindly, find the attached picture. Thanks in advance.
  16. Well as the title says its pretty straight forward. I would like to connect a Master Port from PS to a Slave Port of the MB (PL), such that i can send data from PS to MB, but i cannot see where to enable them. Thanks for any kind of advice
  17. So my current project is very simple, but I've yet to settle on how the control logic is going to be implemented. I think the FSM and Microblaze are both perfectly viable solutions, but I want to find the intersection of maximum learning and minimum complexity. The controller will be performing three tasks: -Pass alternating I and Q data from another module via usb to the user. -Receive data from the user via usb to set a desired frequency. -Interface with the clocking manager to request the new frequency. I am sure I could create an FSM to accomplish this, the USB controller has already been done, my hesitation is a lack of understanding of the AXI4 and DRP interfaces. I am familiar with 8-bit RISC AVR microcontroller, and if given a similar structure, I would think designing with a microcontroller would be almost trivial, but there is surely a learning curve to climb. The question boils down in my mind to a balance between the complexity of the FSM and the learning curve of Microblaze. I also am inclined to say some introductory experience with Mircroblaze would likely be desirable for a future employer. What do you think would be a better opportunity for learning?
  18. Hi, I am trying to get the Microblaze working with the PS hand in hand, i.e. some program is running on the PS and some of it tasks should be outsourced to the Microblaze. My question is how do I need to connect the Microblaze with the PS such that this communication possible ? Some guide/tutorial would be awesome. Thanks!
  19. Hi , I am confronting dimensions mismatch in my design . So could I solve this issue by manipulating the dimension of PmodDA3_0 (pin : AXI_LITE_GPIO_wdata[31:0] ) , and keeping the rest of my design untouched ? If yes , how ? If no, what should I do? Kindly see the attached picture . Kind Regards
  20. Ahmed Alfadhel


    Hi , I have encountered this error during runnuing Vivado Simulator : "formal port ja_pin3_io of mode inout cannot be associated with actual port ja_pin3_io of mode out " What I can do for avoid this error ? Kind Regards
  21. Hello everybody, I'm new to this forum and to fpga programing and I got a question: is it possible to implement a linux on microblaze and having non linux-managed blocks (classic logical blocks) at the same time? and how to realize that. I got the webpack suite of Xilinx (vivado + sdk), i'm working on windows but got a ubuntu virtual machine ready. To define the project, a little draw: For the linux implementation, i found @loberman manual, i was close by myself but it's realy helpfull. Thanks guys
  22. Hi all, I've built with the Nexyx4 DDR board a system running Linux. In my running HW design, I've added the onboard temperature sensor of the board and the PMOD A connector to connect a I2C TMP3 temperature sensor. The HW interface for the onboard temperature sensor is the AXI IIC interface. For the TMP3 sensor with the Digilent's vivado library (as explained in:, it's the AXI LITE IIC interface. With the Linux I2C tools, I see the onboard sensor: nexys4ddr:/# uname -r 4.14.0-00493-gb68293ad2c93-dirty nexys4ddr:/# i2cdetect -y 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- 4b -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- And I can read temperature with the Linux I2C API: nexys4ddr:/# tsttemp TEMP=29.2 oC nexys4ddr:/# But I don't see the I2C TMP3 sensor. My questions are: - The vivado TMP3 instance has a I2C interface (AXI LITE IIC). Can I use the Linux I2C API? If yes, on the PMOD ja port, what are the pins of the connector corresponding to SCL, SDA (easy for ground and 3V3 ;-)? I didn't find this information in the Digilent's vivado library. - If I I can't use the Linux I2C API, I must generate by hand and by software the SCL and SDA signals and what is the role of AXI LITE IIC interface? In this case, would it better to use directly the IIC AXI interface as with the onboard sensor and precise after in a XDC file connexions between to the PMOD A port and TMP3 sensor? Thank you for your help. Pat.
  23. Hello, What is the status with the the FreeRTOS running on a FULL implementation of a Microblaze on ARTY ? I bought this board for this specific purpose following your presentation video : Regards
  24. Hello! I'm using an Arty-S7 with a PMODOLED. I want to draw several rectangles on the little display, but the example design seems to delete the previous rectangle when I add a new one. Is there some magic to display multiple rectangles or do I need to dig deeper and hack on OledGrph.c? Thanks! Craig