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  1. Hello, I checked the tutorials and read the pdf-s on the AXI Interrupt controller. However, i could use come clarification about a couple of things. In Microblaze advanced configuration there's an option to set interrupts to NONE/NORMAL/FAST, or leave it in AUTO mode. Is this setting linked to the AXI interrupt controller creation process? I mean if it run Block Automation, and enable Interrupt Controller, then AXI Interrupt Controller IP is created, but the setting doesn't change in the microblaze settings (for example it stays AUTO/NONE). Does that mean if i want a normal
  2. Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with mic
  3. hello, i am implementing image processing on Xilinx Basys 3 board for which i am using microblaze. I have created an image processing ip which will be reading and writing data through a DMA to microblaze. But i not not sure which is the right way to connect my DMA to microblaze. If i am using Zynq PS i would be using HP mode or slave ACP pin to connect with my DMA but have no idea how to do the same in MicroBlaze.
  4. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  5. Just like this post here, my out of the box example's ethernet is not working. In trying to follow the guide. Changed link speed to 100 as it said. The echo server isn't working, keeps saying the link is up then down, and my computer keeps connecting then disconnecting. All within about a second, so I don't have nearly enough time to see if anything is working even when it is "connected". So then I tried the peripheral test project, and I got an "AxiEthernet: Rx fifo over run" on the "AxiEthernetSgDmaIntrExample". So I increased the rx buffer in the IP re-customization to the max 32KB, no
  6. I have an old Spartan 3E Starter Kit and I need to develop an embbeded system. Such system targets an acceleration for a specific computation process. https://i.postimg.cc/0QDXmRBb/image.png To do so, I will employ MicroBlaze for the management process connected to a vhdl block which is the piece of hardware that will perform the acceleration itself according to Figure 1. Figure 1 - basic scheme for my acceleration process The design is being done in XPS (the hardware) and in Eclipse SDK (the software). In the C soft
  7. Hi, I am playing with the nexys video user demo. I have changed the bitstream to display an overlay (BITC) instead of mouse pointer, and I can bake the bootloader into the bitstream and write it to the flash. I now want to change the microblaze software, which appears to be at flash address 0xa00000. What format image do I write there? Is it the ascii SREC file? James
  8. dfdias

    AXIQUADSPI-ACL-NEXYS4

    Hi was trying to interface the accelerometer available on the nexys 4 board. But i was not getting any data. Then I mapped the output pins to the JA PMOD header so I could probe them Using an logic analyzer I saw that the sclk and Chip_select were working but the MOSI signal is full of zeroes. I connected an 50MHz clk coming from the clock wizard, and then connected it to the ext_spi_clk and used an scale of 16 so the clk is about 3.16MHz Below is the Block_Design helloworld.c Below is the data I acquired using saleae logic analyzer:
  9. Billel

    Microblaze sleep mode

    Hello How can I put the Microblaze in standby mode and reduce its power consumption? regards,
  10. Hello, I'm a student and currently working on my final project including Basys 3 board and wifi pmod. I'm trying to get started working with the module to understand how it works. This is my first project working with Pmods. I've been using the Getting Started with Digilent Pmod IPs tutorials. I added the newest Vivado library including the PmodWifi IP and I bulit a block design with the MicroBlaze and other GPIO IPs. I followed the instructions of the tutorials and got to the part of validating the design, there I got a warning saying few of the wifi pmod pin are not conne
  11. I am starting with working design for the CMOD S7 where I program the device through SDK and all functionality works as intended. Now where I am falling short is getting the program to run out of the SPI Flash. I have been following the "How To Store Your SDK Project in SPI Flash" guide from Digilent in order to put a Microblaze design into SPI Flash on the CMOD S7 located at the link here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start There is a recommended offset of 0x00300000 for the CMOD A7 - My question is what is the recommended o
  12. Dear Support, I am trying to implement a Microblaze in the Arty S7 with 50T FPGA board revision E. (yes Rev E not B). I instantiate GPIOs, Switches, LEDs, pushbuttons, UART and SPI at J7. I want to write c code to control the LEDs and talk to an SPI device. Attached is my implementation in picture format. The design verifies, synthesizes, and implements, but I get timing is negative. ISSUES 1. I am not sure how the GPIOs route from the block diagram to constraint file. I downloaded the constraint file, and uncomment the clock, and GPIO switches, etc...However, in the blo
  13. Hi I am new to microblaze. I have to design an efficient ALU using microblaze in Nexys 4 Anyone can guide through me the procedure ( I know the general guide line) and refer any document to do it Regards Uzmeed
  14. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin
  15. Hi all, This is a quick and dirty howto. This howto describes how to use I2C modules (onboard and through PMOD connector) under embedded Linux. I've chosen to build my own Linux distro based on Linux kernel source for MicroBlaze softcore and busybox project for the init RAM DISK. My board is the Nexys4 DDR board. If you respect the following requirements for the HW design compatible with Linux, you can use Petalinux too. HW Vivado requirements (according to Xilinx UG1144) design to boot Linux: MicroBlaze with MMU support by selecting either Linux with MMU or Low-end L
  16. Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.
  17. I am following the steps outlined in https://reference.digilentinc.com/vivado/getting-started-with-ipi/start I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor. The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest. [DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/
  18. Hi @jpeyron, Hi all, I want to read data from IOmodule, then send this data to a PmodDA3 module using Microblaze. What is the right procedure to read data from IOmodule ? Kindly, find the attached picture. Thanks in advance.
  19. Well as the title says its pretty straight forward. I would like to connect a Master Port from PS to a Slave Port of the MB (PL), such that i can send data from PS to MB, but i cannot see where to enable them. Thanks for any kind of advice
  20. So my current project is very simple, but I've yet to settle on how the control logic is going to be implemented. I think the FSM and Microblaze are both perfectly viable solutions, but I want to find the intersection of maximum learning and minimum complexity. The controller will be performing three tasks: -Pass alternating I and Q data from another module via usb to the user. -Receive data from the user via usb to set a desired frequency. -Interface with the clocking manager to request the new frequency. I am sure I could create an FSM to accomplish this, the USB controller h
  21. Hi, I am trying to get the Microblaze working with the PS hand in hand, i.e. some program is running on the PS and some of it tasks should be outsourced to the Microblaze. My question is how do I need to connect the Microblaze with the PS such that this communication possible ? Some guide/tutorial would be awesome. Thanks!
  22. Hi , I am confronting dimensions mismatch in my design . So could I solve this issue by manipulating the dimension of PmodDA3_0 (pin : AXI_LITE_GPIO_wdata[31:0] ) , and keeping the rest of my design untouched ? If yes , how ? If no, what should I do? Kindly see the attached picture . Kind Regards
  23. Ahmed Alfadhel

    Pmod

    Hi , I have encountered this error during runnuing Vivado Simulator : "formal port ja_pin3_io of mode inout cannot be associated with actual port ja_pin3_io of mode out " What I can do for avoid this error ? Kind Regards
  24. Hello everybody, I'm new to this forum and to fpga programing and I got a question: is it possible to implement a linux on microblaze and having non linux-managed blocks (classic logical blocks) at the same time? and how to realize that. I got the webpack suite of Xilinx (vivado + sdk), i'm working on windows but got a ubuntu virtual machine ready. To define the project, a little draw: For the linux implementation, i found @loberman manual, i was close by myself but it's realy helpfull. Thanks guys