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Found 45 results

  1. Arty with custom IP

    I have Arty A7-35T and I tried following this tutorial ( to have the Microblaze communicate with custom VHDL. In the C++ file the macro for 'XPAR_MY_MULTIPLIER_0_S00_AXI_BASEADDR' matches what the address editor says. I always 0 from the address that should be the result of the multiplier. I don't know what I'm doing wrong or if anything from the tutorial needs to be done different for the Microblaze.
  2. Hello All, Have been attempting to enable interrupts on a project using the Arty and was running into issues with the intc_SelfTest failing. I loaded the Arty BSD from github thinking I had some issue with the project itself but am getting the same exact result. Any suggestions as to what I may need to change? I changed nothing in the BSD so I'm assuming it should be correct. Also followed multiple online tutorials and have been unable to solve the issue. All suggestions are greatly appreciated. Thx!
  3. No Compatible Board Interface

    Hi, I am using Vivado 2017.2 to create a project that uses a MicroBlaze soft CPU core system for a Zybo development board. The intended hardware design will be enough to be able to create a simple hello world program using the SDK. There will be UART and evuntually some GPIO to interface with the boards LEDs and switches etc. I start by adding a MicroBlaze IP to a blank block diagram. Then I run Block Automation and accept the default settings. In the TCL console I get the following info message. INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI What does this mean and do I need to do anything to correct this? Any help would be appreciated. Regards FarmerJo
  4. Arty XADC external voltage input

    Hello, I am using the microblaze system with the xadc on an Arty board. I'm able to successfully read the internal voltages and temperatures of the chip, and I made some external pins (such as the VP/VN and Vauxp0 and Vauxn0). The pins which are external have been connected in a constraints file. My power supply positive terminal is hooked into the A0 port on my arty board, and the negative terminal is hooked into a gnd port. The XADC is attached to the AXI lite bus, controlled by the microblaze. Please let me know if any of this is unclear. P.S. I've looked into the spec sheets but am still a beginner so I'm not always successful finding the right information. Greatly appreciate the help! Nystflame
  5. Arty Microblaze SPI J6 Header

    Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design. I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers). Regards, Nystflame
  6. BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  7. Hi, Is there a good example to establish communication between Zynq and Microblaze processor on Zybo? I am looking to understand how to get both these processors to talk to each other, share data etc. I'm aware of this Xilinx app note: But i'm looking for something simpler and on Zybo. Thanks.
  8. Multiple UARTLite Instantiation w/ Microblaze

    Trying to instantiate multiple UARTLite cores in a microblaze design using an Arty Board. For some reason, the output of both UARTLite modules is going through the same USB UART port as opposed to the second port I've configured. Any suggestions? [CONSTRAINTS] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_rxd] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN U11 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN V16 [get_ports usb_uart_bc127_rxd] [SOURCE CODE] #include "xparameters.h" #include "xstatus.h" #include "xuartlite.h" #include "xil_printf.h" /************************** Constant Definitions *****************************/ #define UARTLITE_DEVICE_ID_0 XPAR_UARTLITE_0_DEVICE_ID #define UARTLITE_DEVICE_ID_1 XPAR_UARTLITE_1_DEVICE_ID #define TEST_BUFFER_SIZE 16 int UartLitePolledExample(u16 DeviceId); /************************** Variable Definitions *****************************/ XUartLite UartLite_0; /* Instance of the UartLite Device */ XUartLite UartLite_1; /* Instance of the UartLite Device */ /* * The following buffers are used in this example to send and receive data * with the UartLite. */ u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ int main(void) { int Status; /* * Run the UartLite polled example, specify the Device ID that is * generated in xparameters.h */ Status = XUartLite_Initialize(&UartLite_0, UARTLITE_DEVICE_ID_0); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } Status = XUartLite_Initialize(&UartLite_1, UARTLITE_DEVICE_ID_1); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran Uartlite polled Example\r\n"); //XUartLite_Send(&UartLite_0, SendBuffer, TEST_BUFFER_SIZE); int temp = 80000; int simplecounter = 0; char links[] = "DIGILENT DIGILENT\n\0"; char linksx[] = "ARTY ARTY ARTY ARTY\n\0"; while (1) { if (1) { xil_printf("Cha Cha Cha.... %d\r\n", simplecounter++); XUartLite_Send(&UartLite_0, &links, TEST_BUFFER_SIZE); XUartLite_Send(&UartLite_1, &linksx, TEST_BUFFER_SIZE); temp = 80000; } } return XST_SUCCESS; } [XPARAMETERS] /* Definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0 #define XPAR_AXI_UARTLITE_0_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8 /* Definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_AXI_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_AXI_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_AXI_UARTLITE_1_DEVICE_ID 1 #define XPAR_AXI_UARTLITE_1_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_1_USE_PARITY 0 #define XPAR_AXI_UARTLITE_1_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_1_DATA_BITS 8 /******************************************************************/ /* Canonical definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID #define XPAR_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_UARTLITE_0_BAUDRATE 9600 #define XPAR_UARTLITE_0_USE_PARITY 0 #define XPAR_UARTLITE_0_ODD_PARITY 0 #define XPAR_UARTLITE_0_DATA_BITS 8 /* Canonical definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_UARTLITE_1_DEVICE_ID XPAR_AXI_UARTLITE_1_DEVICE_ID #define XPAR_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_UARTLITE_1_BAUDRATE 9600 #define XPAR_UARTLITE_1_USE_PARITY 0 #define XPAR_UARTLITE_1_ODD_PARITY 0 #define XPAR_UARTLITE_1_DATA_BITS 8
  9. How to add own logic to Arty board flow?

    The Arty board examples and tutorials use the Vidado drag and drop editor. But, there is no example how one would add their own custom logic. I have hacked this so far by dropping a peripheral and then replacing the stub verilog file, but it would help to show how this should be done. The natural would be to drop in a custom bus i/f file (e.g. using the AXI to AHB or AXI to APB bridge to a stub) and also how you add pins to the port list. Hacking away at it seems just wrong - if there is some intended flow, it is not apparent. The old way of editing the .ucf file and adding the ports to the top file does not seem like a fit for this SDK/Microblaze environment. Thanks, Paul
  10. Running XAPP1093 on Zybo

    I am trying to run something akin to the Xilinx 1093 profile. I want to have bare-metal apllications on both the ARM A9 and the Microblaze co-processor. In the SDK, I created a Zynq FSBL and three separate simple Hello World application projects, for CPU0, CPU1 and Microblaze. When I debug the application, I download all three of these projects to the FPGA. But I only see a Hello World from Microblaze and CPU1 on the terminal. If I don't download the CPU1 project, then I can see the Microblaze and CPU0 Hello Worlds just fine. I have attached the tcl script for the block design I used. As far as the application projects, they are the simple auto-generated hello world .c files from the SDK. What prevents CPU0 from sending Hello World to the terminal when the project for CPU1 is also downloaded? My end goal is to run either an image processing or an encryption algorithm, that divides tasks between the two cores and Microblaze or the ARM processor in general and Microblaze. 1) Should something change or be added to the block design for this to happen? 2) Is the communication between ARM and MB achieved through functions in the .c files? design_1.tcl
  11. Memory issues in Arty-7x Microblaze

    I'm working on some embedded software on the Arty board and programming in Microblaze. When I try to allocate an array of sixteen-bit numbers, length 512, it works just fine, but the same array set to length 1024 causes malloc to return NULL. After some experimentation and testing, I believe this is because the Microblaze processor has run out of internal memory. However, the Arty board is supposed to have 256MB of DDR memory. An interface to the memory already existed in my block diagram (copied from Getting Started With Microblaze with some PMods added), so I assumed that the DDR memory was already being used by the Microblaze processor, but 256 MB of memory shouldn't be struggling to deal with a 2KB array. (Outside of the allocated array, the program is very small.) Is there something special I need to be doing to access the DDR memory from inside Microblaze?
  12. I've done quite a bit of work with using the Cortex A9 on the Zeboard, and as such am at home in the tools flow. I also have a Nexys4 DDR, and need a processor for a project I'm working I figured I'd give the Microblaze a whirl. I did the Hello World tutorial that is on the Digilent site...pretty straightforward, except for one strange bit of behavior: When I run my hello world app, main runs twice, both in debug and release mode. I stepped through the code, and it appears that somewhere in cleanup_platform(), main gets invoked again (recursively). This ends up running init_platform() again, as well as printing my message to the screen twice. I am going to see if I can track down where in cleanup_platform() this is happening, but was wondering if somebody else has seen this, and can offer an explanation and/or fix? My design is completely according to the tutorial right now...I haven't added any of my own HW logic or additional SW code yet. UPDATE: I did some further debugging, and it looks like this happens during the call to Xil_ICacheInvalidate() (xil_cache.c). Getting more specific is difficult as it appears to happen some time during the loop in microblaze_invalidate_icache.S line 70. I'm no expert with the MB ISA yet, but can certainly deduce that this is walking each cache line, and I'm assuming, marking them as invalid. While doing this debugging, I actually got the processor into a state where this recursive call into main would continue as long as I'd let it, each time, printing out a new message. Very strange. Thanks, Dave
  13. clock mismatch in IP integrator

    HI there, I have a simple HLS design which I exported as an IP Core to implement on my target. But I get the following error when I go ahead interconnecting the IP cores. Does anyone have any idea as to how I can work around this obstacle? I even tried changing the frequency of the ports, but the fields are inactive. [BD 41-237] Bus Interface property FREQ_HZ does not match between /matrixmul_0/INPUT_STREAM(100000000) and /axi_dma_0/M_AXIS_MM2S(200000000) [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_dma_0/S_AXIS_S2MM(200000000) and /matrixmul_0/OUTPUT_STREAM(100000000)
  14. Hello all, I wish to receive 10 Mb of data through Ethernet using TCPIP protocol. I am newbie to LWIP so use Microblaze server demo code for reference. The problem i faced is i only able to receive 1460 bytes of data with echo server example code. I also added pbuf_copy_partial() function and specified pointer where data should be store but when i try to read data from pointer specified i am getting some garbage values. i also acknowledge packet reception but still i would't able to fix issue. i have also attach snapshot of code which i modified please suggest steps for data reception. Regards, Kumarkk
  15. Hi, I have a simple design. In an ARTY board, I need to read from ddr3 initialized in SDK and write to pmod constantly in a loop. What is the recommended way to do this? Do I need to use the DMA? Is there a reference design for ARTY board? Thanks
  16. Hi Mr./Ms., I have successfully make Nexys Video Microblaze server example works following: However, the echo server only works under standalone OS but not xilkernel OS. It gives me the error "unable to alloc pbuf in recv_handler" called from "setup_rx_bds" function, even I haven't telnet the server yet. I have tried: 1. increase heap size 2. increase pbuf_pool_buffer size, pbuf_pool_size 3. increase mem_size, mem_n_pbuf 4. enable jumbo frame 5. increase TX and RX buffer size in axi_ethernet component in vivado The enlarged men size can delay the appearance of this error, but error message still come out and I cannot echo successfully. I guess it is not a pure problem from memory size since standalone works, maybe because the xilkernel is too busy so that cannot catch up with the speed of coming packets. So far the speed of LINKSPEED is also 100MHz as well as sys frequency. I wonder any way can slow down the coming packets ? PS: board is Nexys video, vivado is 16.2, xilkernel is 6.3, lwip is 1.4.1 Thank you very much!
  17. Hi, I am using Nexys Video board and fail to trigger interrupt to Microblaze in SDK. So I generate a basic project with only AXI timer, and test with "Peripheral Test" application for xilkernel in SDK, but the test fails as well. In Vivado: 1. select the board and create a block design. 2. add microblaze with interrupt controller. add axi_timer and uartlite. 3. connection as attached figure: ": 4. enable Microblaze exception. generate bitstream. In SDK: 1. generate bsp for xilkernel, and generate an application of "Peripheral Test" in template, and run. Fail when running "Interrupt Test for axi_timer_0" as shown in figure: In fact, I have tried to interrupt from IP generated by vivado AXI interrupt wrapper, or from customer IP (generated interrupt interface myself), no matter with SENSITIVITY being EDGE_HIGH or LEVEL_HIGH, no matter with concast component or single interrupt, no matter enable exception in bsp or microblaze, neither of them succeed in calling my handler. I believe this is not the problem in software (I register handler and enable all interrupts), and even the template application based on basic components still not work. Did I miss anything? Thank you very much! Cynthia
  18. DDR3 configuration

    Hello Everyone, This is Vishnu , FPGA Design Engineer. I need help from you, in my project I need to get data into DDR from camera and has to given for another data processing module. Here I have some doubts regarding storage . 1) As camera is line scanning camera , Is it possible to store line information from camera (line-by-line) and to access it full line-by-line directly.(data is of 12 bit). 2) How many cycles will be delayed if configuration is done with Microblaze . 3) Help me out some links for the configuration to do in customized version. Thanks in advance. Regards Vishnu
  19. VHDL read from BRAM

    Hi, I have a block design with a microblaze, a BRAM, and a custom ip (VHDL). With the custom IP, I have 4 separate signals that will read at the same time from 4 consecutive rows in the bram and output the values. I'm having trouble figuring out how to read 4 separate signals from a single BRAM at the same time. Any advice is much appreciated. Thanks, Vic
  20. PModMic and Microblaze

    I have a PmodMIC3 I would like to use with my Microblaze processor on a digilent Arty board. While trying to get the two devices to communicate through Vivado and the Vivado SDK, I have several questions that I could not find answers to. First, I assume that since there is no specific PmodMIC3 IP block, I should be using the generic PmodBridge IP block in Vivado. The 6-pin PmodMIC3 is plugged into the top row of the 2x6 Pmod output port, so the PmodBridge has it's top row interface set to SPI and the bottom row set to 'Disabled'. The PmodBridge then leads to the AXI Quad SPI block, which is one of the many things going into the Microblaze's AXI Interconnection block. (I assume that the ext_spi_clk on the Axi Quad SPI is meant to be the same ~50 MHz clock as the ext_spi_clk on the PmodOLEDrgb block, also included in this project.) Assuming that this set of connections is the 'proper' way to get PmodMIC3 to communicate with the Microblaze processor, is there any sample code I can look at, even just to see how to configure the SPI for the microphone by setting up the XSpi_Config block in Microblaze? I've been trying to reverse-engineer it from how the PmodOLEDrgb (which works fine)'s sample code uses SPI to communicate, but haven't had success yet.
  21. Hi: I was wondering if anyone has used the MicBlaze - AXI based access to the XADC to communicate with the AUX4 (XSM_CH_AUX4??) and AUX12 (XSM_CH_AUX12??) channels. Based on my read of the and the comments, I guess the CMOD A7 analog inputs to be the XSM_CH_AUX 4 and 12 channels. I seem to be missing something with regards to how to initialize them. Thoughts? Peter
  22. MicroBlaze 40 cycles per instruction?

    Hi, I have been trying the MicroBlaze tutorials for the Arty board and while adding some logic to them I noticed things running quite slow. I measured a tight loop and it looks like it's taking 40 cycles per instruction. To confirm I used the "Performance Analysis" in the Xilinx SDK and I got the same number. I have instruction and data caches and I don't see how is this possible. What can I be missing here? Thanks!
  23. I want to use the flash memory of 32Mbits of the basys 3, to write data in hexadecimal, I am using microblaze and the IP block axi quad spi, I have configured the hardware in vivado, i have included the soft-core microblaze and I have added the IP block Axi_quad_spi and I have connected the ext_spi_clk, s_axi_aclk (synchronously), with the 100 MHz clock, automatically vivado connected the outputs to the pins of the flash memory of the basys 3 card, so my question is: to program the memory in the SDK of xilinx, is there an example already done with this memory ?, or how can i program it?
  24. TCL script in tutorial out of date

    In order to figure out how to connect the on-board switches, buttons, and LEDs to Microblaze, I tried to follow the instructions in this Learnable. Sadly, the 'create_project.tcl' script seems out of date and can't be used to create a board design. I get the following error messages - ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.3> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.3>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script. ERROR: [BD 5-229] Please open or create a block design first. ERROR: [Common 17-39] 'get_bd_designs' failed due to earlier errors. while executing "get_bd_designs" invoked from within "set design_name [get_bd_designs]" (file "./create_project.tcl" line 106) Trying to run the entries in the create_project.tcl one at a time, or one at a time after creating and opening a block design, also failed with similar messages. Is there something obvious I'm missing? Could I get an updated version of the script?
  25. Expanding BRAM for a Microblaze application

    I'm working with a Kintex-7 board. Currently my application relies on external DDR, but I want to turn it entirely off internal memory on the FPGA. From what I have gathered online, this is possible to do, but haven't been able to find a clear answer on how to do this with the modern SDK. I can change my linker script to allocate more memory to BRAM and the program will compile. But I"m having trouble in Vivado when trying to generate required hardware with enough memory. I have Microblaze with the following ports: DLMB (data mem) <---> LMB <----> LMB BRAM Controller1 <---> Block memory gen 1 ILMB (instr mem) <-----> LMB <----> LMB BRAM Controller2 <---> Block memory gen 1 AXI_DC (data cache) <-----> External DDR AXI_IC (instr cache) <------> External DDR I want get rid of the external DDR from the design, but the program is too large to sit in the default BRAM allocated size of 32k x 32b wide. Seems like this is hard limit for one block, but it is possible to cascade more to expand the depth. I have verified that there is way more than enough total BRAM in the FPGA to store the program. In Vivado, Has anyone be able to do this or knows how it can be done?