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Found 62 results

  1. Hello all, I have a question pertaining to my ZedBoard. I'm running Linux on the PS using the built in SD card slot. I'm simultaneously building an isolated system in the PL, currently consisting of a Microblaze running a baremetal application. Now I'd like to run Python in the PL without touching the PS setup. Could I use the SD card Pmod to persist Linux to run on the Microblaze? I know I can't touch the existing SPI since it belongs to the PS, and I'd also like plenty of storage. Thank you for your time
  2. Dear all, I'm still working on a example design where I've a microblaze, one UART, some RTL logic defined by VHDL files and connected to the Microblaze. Now I'm try to connect some signal to some output of the Cmod A7-35T board. Here the schematic: Concerning the sys_clock I can see the constraints into the board file for the Cmod A7-35T board hence I think this is ok and no need to specify it directly. About the others pin, in order to connect it to a FPGA pin I've used this procedure: - select a pin and then make a right-click - from the menu select the Make External menu entry this make a port with a default name liek the one used into the output pin of the logic block where the pin came from. Now I've to associate a logical pin with a hardware pin of the FPGA. to do that I've loaded as new contraints file the xdc board files provided by Digilent and then I've unmarked the following lines: then I've changed accordling these names the one on the graphicl view in order to match the one into the XDC file. To change the name assigned as default to a pin into the graphical view of the system I've do right click on the port and then I've selected the External Port Properties menu entry. On the left side of the design view I've changed the default pin name with the name that I can found into the XDC file for the pin that I've choose to use, in this example the pio4 pin. QUESTION #1 Now I'm asking to expertes if my steps are correct in order to setup all the input/output physical pins used into a design. QUESTION #2 About the reset pin that is used for the MMCM generated by the Block Design when I've configured the microblaze for the first time I've a doubt, this pin is not listed into the XDC file board provided by digilent then I've to assign it to an external pin, like a pushbutton or this special signal is assigned internally to the reset circuitry of the FPGA? Where I can found more info on the subject? QUESTION #3 There is a way to see the options used for the Microblaze soft core on the first wizard definition and then change it after the first definition? Thank for your time and help. Best regards
  3. Hello, I am using Arty board attached to 2 peripheral modules (PmodSD and PmodNAV) to write navigation data to SD card. To do so, I am combining the C example codes provided on Github for each module, and simplified it a bit which is attached. My problem is that each one of the modules are working fine individually with their own code, as long as the other Pmod is not initialized in the C code, but when I am using them at the same time it destroys my output to terminal and writes zero to both terminal and SD card. I am suspicious that the issue is because PmodSD and PmodNAV are both using AXI_LITE_SPI to talk to Microblaze, and I do not have any control on SPI bus when I am writing data. As a result, Microblaze does not know how to communicate with both of Pmods at the same time. Does this make sense? What is the best way to control the AXI_LITE_SPI when there are multiple modules connected to the Microblaze? I am trying to keep this as simple as possible, so I can use the example codes. Any help is highly appreciated. -Mahdi main.cc
  4. bgwbogdan

    locked signal is not high

    Hello to all, I'm facing really strange problems with Arty7 Artix board. In some cases when I generate .bit file for my microblaze design, there is no locked signal from the clocking wizard. Please check attached image. Input of clocking wizard is directly connected to E3 pin and "locked" signal is connected to the one of the board's LEDs. The rest of my design is composed of MicroBlaze instance with Ethernet IP core, MIG, UART, SPI flash core and "glue" logic for these components. I'm using Vivado 2017.2 or 2018.1, win 10 x64, win 7 x64, no matter. Input clock is present, I have check it by using scope, seems to be OK, .xdc file is correct. No critical warnings or timing issues, nothing special in my warning list. Simply, in some cases there is no locked signal from the clocking wizard.. Any help is highly appreciated, I'm out of ideas... Thanks!
  5. Hi there, I'm using Arty 35 and when I select the MicroBlaze MCS IP from the Ip catalogue I get to a Menu where I can "assiociate IP interface with board interface" and for the IP Interface GPIOx I can chose "shield do0 to dp19" or "shield dp26 to dp41" (beneathe other) and I'm wondering if somebody could tell me what parts of the board exactly that option is referring to? I assume "shield" referres to those pins on top of the board and dp26 to dp41 are probably labeled as IO41 - IO26 of J4 and J2 but whats the rest? And if I instanciate those GPIOs like that, does it mean I there will be an adress created that I can use in sdk then to read/write from/to those pins? thx! thanks!
  6. Hi Mr./Ms., I have successfully make Nexys Video Microblaze server example works following: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start However, the echo server only works under standalone OS but not xilkernel OS. It gives me the error "unable to alloc pbuf in recv_handler" called from "setup_rx_bds" function, even I haven't telnet the server yet. I have tried: 1. increase heap size 2. increase pbuf_pool_buffer size, pbuf_pool_size 3. increase mem_size, mem_n_pbuf 4. enable jumbo frame 5. increase TX and RX buffer size in axi_ethernet component in vivado The enlarged men size can delay the appearance of this error, but error message still come out and I cannot echo successfully. I guess it is not a pure problem from memory size since standalone works, maybe because the xilkernel is too busy so that cannot catch up with the speed of coming packets. So far the speed of LINKSPEED is also 100MHz as well as sys frequency. I wonder any way can slow down the coming packets ? PS: board is Nexys video, vivado is 16.2, xilkernel is 6.3, lwip is 1.4.1 Thank you very much!
  7. Ben_Cook

    Nexys Video HDMI Demo boot from QSPI Flash

    Hello, I have a Nexys Video board and I have successfully loaded the “Nexys Video HDMI Demo”. I followed the tutorial "Using Digilent Github Demo Projects" to install and run the project through Vivado and SDK. I would like to learn how to get this demo to boot from QSPI flash following initial application of power to the board. I tried to follow this tutorial “How To Store Your SDK Project in SPI Flash". However, I get stuck creating the bootloader at step 1.2 as I do not have the option to use the ‘SREC SPI Bootloader’ template. When I try to select SREC SPI Bootloader, the SDK throws the following error: “This application requires a AXI Quad SPI in the hardware.” At this point, the ‘Next’ and ‘Finish’ buttons are greyed out, so I hit a dead-end. Could you please advise how I would go about storing this demo in SPI Flash? Many thanks in advance, Ben Cook
  8. abcdef

    BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  9. Thausikan

    How to connect DMA with microblaze ?

    Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  10. liwerfm

    Microblaze inputs

    Hi, I'm new in FPGA. I have a design with vivado ipi and i don't know how to interact with an input hardware signal at the microblaze. I know that if the signal is external of the hardware, i can use GPIO module, but i don't have any idea of how do it with internal signals
  11. Hello guys, I am fairly new to FPGAs, but I have managed to get my Arty board to work with a bunch of Pmods through Vivado software with MicroBlaze. At this point, I am trying to use AXI Quad SPI for collecting data from an external ADC. I have my own 16-bit ADC (connected to a detector) which has an event flag pin that goes high when an event is detected. The flag is supposed to be latched high until the CPU responds and shifts out the 16-bit value. I wonder how can I implement such design inside my block diagram? I tried adding a SPI connector to my diagram, but as far as I see there is no pin on SPI block that I can connect my event flag to. Any help is highly appreciated. Mahdi
  12. Hi, PRBS data from 1st board--> LVDS out (data)--> LVDS in (data)--->2nd board-> Aurora Tx (2nd board)-> Aurora Rx (1st board). Almost, i have completed the first part (1st board side), but in second part i dont know how to connect the IBUFDS(LVDS in) with microblaze and FIFO setup. Because IBUDS does not have AXI kind of connections. Please anyone guide ma.
  13. Hi, I have integrated simplex TX aurora block and simplex RX aurora blocks into a single design through a loop-back in order to make duplex mode. But while simulating the XSDK codes, TX length and RX length are mismatched. I am working with Kintex development DAQ board [xc7k160tffg676-2], and i have attached the BD design in which TX and RX are make into external. Where i am going wrong i don`t know, please point out and guide me. Please find the attachment of BD diagram. Thanks
  14. Weevil

    Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dds-compiler over the Stream-Data-FIFO to the FFT right?
  15. Hello, I am following this tutorial for microblaze for the nexys 4 ddr: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start?redirect=1 I am getting an error for the mig_7_series... generation that is outlined when I try to generate the bitstream in step 14. It looks like it is pulling the mig from Xilinx's core generation, is it supposed to be using the mig from the nexys 4 ddr files instead? Here is my error output: Another thing to note, I have a space in the directory path, is that the issue possibly? It is not complaining about anything else though. I have also verified that the file it "can't find" is actually there and has contents. I'm running Vivado 2017.4 WebPack, but I can't imagine this would cause issues for a Xilinx IP core, maybe for IP cores from Digilent. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 . error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.4/data/ip/xilinx/mig_7series_v4_0/xit/synthesis.xit': error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s). ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_mig_7series_0_81M .
  16. Hello. I have developed a Microblaze project based on a Digilent Vivado 2016.4 project for the Arty board that I downloaded a year ago. (microblaze server I believe). Everything works in Vivado 2016.4, I can go through the entire implementation to bitstream and SDK export. When upgrading to Vivado 2017.4, I get these errors referring to some encrypted files. In reference to error [Synth 8-5809] I have found this not-to-helpful answer record, referring to FLIT width in an XHMC IP that I dont think is eve nin the project, with no information on how to change it. https://www.xilinx.com/support/answers/68421.html Regarding the second error [synth 8-285] I found this, which claims the problem was in 2016.2, but still appears, so I am skeptical of this solution. Was the default changed back to OOC per IP with 2017.4? I am not sure what generate_target means or does, or when it is processed in the GUI workflow. So I am not sure when to do this in the workflow or what it will do. https://www.xilinx.com/support/answers/68238.html In Vivado 2016.3 there was a change to the default BD generation mode. The default was changed from Global to Out of Context (OOC) per IP. You will not typically see this problem when migrating an existing project because the migration script will maintain the existing generation mode setting. However, in a scripted flow where the entire project or design is being recreated, the new default settings would apply unless explicitly changed. Additionally, the "OOC per IP" BD generation is not allowed in non-project mode. Therefore, starting in Vivado 2016.3, if you are using a scripted non-project mode, you will need to set the BD generation back to global. To do this, set the synth_checkpoint_mode to None (Global synthesis) before generating targets. For example: set_property synth_checkpoint_mode None [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] generate_target all [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] Can someone assist me in this upgrade? I imagine Digilent will be upgrading their example projects at some point. Now would be a great time! Thank you!
  17. Nystflame

    AXI DMA and Microblaze

    Hello All, I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples. I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the transfer length to be. But if I do another transfer, and all subsequent transfers from then on, they seem to be equal to the length which was programmed. I initially thought that this was a caching issue (and still may be), but I've since disabled caching in the software. I've also provided an image below of my Microblaze, and to my understanding there is no caching enabled (i've disabled cache when configuring the Microblaze in vivado). The type of DMA transfer that I am using is just a register direct transfer, not scatter gather. The M_AXI_DP is connected to an AXI Interconnect, of which the M_AXI port of the interconnect is connected to the S_AXI_LITE port of the DMA. Another interesting thing I've noticed is that, if I do an acquisition of ADC samples, read the DDR starting at address 0, and perform another read of DDR starting at address 0, it looks like the data at address 0 updates, but the following data is the same as the first read. P.S. I am still new to Digital Design, sorry if I've omitted any crucial information.
  18. Dear all, i am really new in working with FPGA's and started with some microblaze application. So i build up a standard microblaze system with uartlite and some LED's. Also i generate a sine wave with the dds-compiler and now i want control the input clock of the dds-compiler for changing the output frequency. For this i started to use the axi-Timer (i don't know this is the best way for an adjustable clock) and started to write a C programm in the Vivado SDK software. Till now i don't get any output from the axi-Timer, maybe someone can help me... Thank you! Following the C-code with already working LED's and uart communication:
  19. Nystflame

    Arty Microblaze Speed Question

    Hello, Without implementing a timer, I had thought that toggling a GPIO pin and observing the result via a logic analyzer(has 100Megasample/sec). The Microblaze input clock is coming from the "ui_clk" from the MIG, which seems to be 83 MHz, but when observing the pin toggle the frequency is ~37 kHz. My method for toggling the pin is just an infinite while loop with two Xil_Out32 commands, one for turning the pin on, and the other command turns it off. Any debugging methods I should try as to why the frequency of this switching is so low? p.s. I've since moved from toggling via the xil_out function and am targeting the address of the GPIO pins directly, the frequency I'm seeing now is 130.7kHz, still nowhere near the 80MHz I had been expecting. p.s.s. I've enabled caches and tried block ram vs ddr and the max i've gotten to is 1.3Mhz The following is all of the code in my program for this test: #include "platform.h" int main(void) { init_platform(); volatile unsigned int *pins = (volatile unsigned int *) 0x40000000; for(;;){ pins[0] ^= 0x1; } cleanup_platform(); } Best Regards, nystflame
  20. Hello All, Have been attempting to enable interrupts on a project using the Arty and was running into issues with the intc_SelfTest failing. I loaded the Arty BSD from github thinking I had some issue with the project itself but am getting the same exact result. Any suggestions as to what I may need to change? I changed nothing in the BSD so I'm assuming it should be correct. Also followed multiple online tutorials and have been unable to solve the issue. All suggestions are greatly appreciated. Thx!
  21. jello_cat

    Arty with custom IP

    I have Arty A7-35T and I tried following this tutorial (http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html) to have the Microblaze communicate with custom VHDL. In the C++ file the macro for 'XPAR_MY_MULTIPLIER_0_S00_AXI_BASEADDR' matches what the address editor says. I always 0 from the address that should be the result of the multiplier. I don't know what I'm doing wrong or if anything from the tutorial needs to be done different for the Microblaze.
  22. FarmerJo

    No Compatible Board Interface

    Hi, I am using Vivado 2017.2 to create a project that uses a MicroBlaze soft CPU core system for a Zybo development board. The intended hardware design will be enough to be able to create a simple hello world program using the SDK. There will be UART and evuntually some GPIO to interface with the boards LEDs and switches etc. I start by adding a MicroBlaze IP to a blank block diagram. Then I run Block Automation and accept the default settings. In the TCL console I get the following info message. INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI What does this mean and do I need to do anything to correct this? Any help would be appreciated. Regards FarmerJo
  23. Nystflame

    Arty XADC external voltage input

    Hello, I am using the microblaze system with the xadc on an Arty board. I'm able to successfully read the internal voltages and temperatures of the chip, and I made some external pins (such as the VP/VN and Vauxp0 and Vauxn0). The pins which are external have been connected in a constraints file. My power supply positive terminal is hooked into the A0 port on my arty board, and the negative terminal is hooked into a gnd port. The XADC is attached to the AXI lite bus, controlled by the microblaze. Please let me know if any of this is unclear. P.S. I've looked into the spec sheets but am still a beginner so I'm not always successful finding the right information. Greatly appreciate the help! Nystflame
  24. Nystflame

    Arty Microblaze SPI J6 Header

    Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design. I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers). Regards, Nystflame
  25. Hi, Is there a good example to establish communication between Zynq and Microblaze processor on Zybo? I am looking to understand how to get both these processors to talk to each other, share data etc. I'm aware of this Xilinx app note: https://www.xilinx.com/support/documentation/application_notes/xapp1093-amp-bare-metal-microblaze.pdf But i'm looking for something simpler and on Zybo. Thanks.