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Found 55 results

  1. Hi, PRBS data from 1st board--> LVDS out (data)--> LVDS in (data)--->2nd board-> Aurora Tx (2nd board)-> Aurora Rx (1st board). Almost, i have completed the first part (1st board side), but in second part i dont know how to connect the IBUFDS(LVDS in) with microblaze and FIFO setup. Because IBUDS does not have AXI kind of connections. Please anyone guide ma.
  2. Hi, I have integrated simplex TX aurora block and simplex RX aurora blocks into a single design through a loop-back in order to make duplex mode. But while simulating the XSDK codes, TX length and RX length are mismatched. I am working with Kintex development DAQ board [xc7k160tffg676-2], and i have attached the BD design in which TX and RX are make into external. Where i am going wrong i don`t know, please point out and guide me. Please find the attachment of BD diagram. Thanks
  3. How to connect DMA with microblaze ?

    Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  4. Nexys Video HDMI Demo boot from QSPI Flash

    Hello, I have a Nexys Video board and I have successfully loaded the “Nexys Video HDMI Demo”. I followed the tutorial "Using Digilent Github Demo Projects" to install and run the project through Vivado and SDK. I would like to learn how to get this demo to boot from QSPI flash following initial application of power to the board. I tried to follow this tutorial “How To Store Your SDK Project in SPI Flash". However, I get stuck creating the bootloader at step 1.2 as I do not have the option to use the ‘SREC SPI Bootloader’ template. When I try to select SREC SPI Bootloader, the SDK throws the following error: “This application requires a AXI Quad SPI in the hardware.” At this point, the ‘Next’ and ‘Finish’ buttons are greyed out, so I hit a dead-end. Could you please advise how I would go about storing this demo in SPI Flash? Many thanks in advance, Ben Cook
  5. Hello, I am following this tutorial for microblaze for the nexys 4 ddr: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start?redirect=1 I am getting an error for the mig_7_series... generation that is outlined when I try to generate the bitstream in step 14. It looks like it is pulling the mig from Xilinx's core generation, is it supposed to be using the mig from the nexys 4 ddr files instead? Here is my error output: Another thing to note, I have a space in the directory path, is that the issue possibly? It is not complaining about anything else though. I have also verified that the file it "can't find" is actually there and has contents. I'm running Vivado 2017.4 WebPack, but I can't imagine this would cause issues for a Xilinx IP core, maybe for IP cores from Digilent. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 . error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.4/data/ip/xilinx/mig_7series_v4_0/xit/synthesis.xit': error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s). ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_mig_7series_0_81M .
  6. Hello. I have developed a Microblaze project based on a Digilent Vivado 2016.4 project for the Arty board that I downloaded a year ago. (microblaze server I believe). Everything works in Vivado 2016.4, I can go through the entire implementation to bitstream and SDK export. When upgrading to Vivado 2017.4, I get these errors referring to some encrypted files. In reference to error [Synth 8-5809] I have found this not-to-helpful answer record, referring to FLIT width in an XHMC IP that I dont think is eve nin the project, with no information on how to change it. https://www.xilinx.com/support/answers/68421.html Regarding the second error [synth 8-285] I found this, which claims the problem was in 2016.2, but still appears, so I am skeptical of this solution. Was the default changed back to OOC per IP with 2017.4? I am not sure what generate_target means or does, or when it is processed in the GUI workflow. So I am not sure when to do this in the workflow or what it will do. https://www.xilinx.com/support/answers/68238.html In Vivado 2016.3 there was a change to the default BD generation mode. The default was changed from Global to Out of Context (OOC) per IP. You will not typically see this problem when migrating an existing project because the migration script will maintain the existing generation mode setting. However, in a scripted flow where the entire project or design is being recreated, the new default settings would apply unless explicitly changed. Additionally, the "OOC per IP" BD generation is not allowed in non-project mode. Therefore, starting in Vivado 2016.3, if you are using a scripted non-project mode, you will need to set the BD generation back to global. To do this, set the synth_checkpoint_mode to None (Global synthesis) before generating targets. For example: set_property synth_checkpoint_mode None [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] generate_target all [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] Can someone assist me in this upgrade? I imagine Digilent will be upgrading their example projects at some point. Now would be a great time! Thank you!
  7. Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dds-compiler over the Stream-Data-FIFO to the FFT right?
  8. AXI DMA and Microblaze

    Hello All, I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples. I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the transfer length to be. But if I do another transfer, and all subsequent transfers from then on, they seem to be equal to the length which was programmed. I initially thought that this was a caching issue (and still may be), but I've since disabled caching in the software. I've also provided an image below of my Microblaze, and to my understanding there is no caching enabled (i've disabled cache when configuring the Microblaze in vivado). The type of DMA transfer that I am using is just a register direct transfer, not scatter gather. The M_AXI_DP is connected to an AXI Interconnect, of which the M_AXI port of the interconnect is connected to the S_AXI_LITE port of the DMA. Another interesting thing I've noticed is that, if I do an acquisition of ADC samples, read the DDR starting at address 0, and perform another read of DDR starting at address 0, it looks like the data at address 0 updates, but the following data is the same as the first read. P.S. I am still new to Digital Design, sorry if I've omitted any crucial information.
  9. Dear all, i am really new in working with FPGA's and started with some microblaze application. So i build up a standard microblaze system with uartlite and some LED's. Also i generate a sine wave with the dds-compiler and now i want control the input clock of the dds-compiler for changing the output frequency. For this i started to use the axi-Timer (i don't know this is the best way for an adjustable clock) and started to write a C programm in the Vivado SDK software. Till now i don't get any output from the axi-Timer, maybe someone can help me... Thank you! Following the C-code with already working LED's and uart communication:
  10. Arty Microblaze Speed Question

    Hello, Without implementing a timer, I had thought that toggling a GPIO pin and observing the result via a logic analyzer(has 100Megasample/sec). The Microblaze input clock is coming from the "ui_clk" from the MIG, which seems to be 83 MHz, but when observing the pin toggle the frequency is ~37 kHz. My method for toggling the pin is just an infinite while loop with two Xil_Out32 commands, one for turning the pin on, and the other command turns it off. Any debugging methods I should try as to why the frequency of this switching is so low? p.s. I've since moved from toggling via the xil_out function and am targeting the address of the GPIO pins directly, the frequency I'm seeing now is 130.7kHz, still nowhere near the 80MHz I had been expecting. p.s.s. I've enabled caches and tried block ram vs ddr and the max i've gotten to is 1.3Mhz The following is all of the code in my program for this test: #include "platform.h" int main(void) { init_platform(); volatile unsigned int *pins = (volatile unsigned int *) 0x40000000; for(;;){ pins[0] ^= 0x1; } cleanup_platform(); } Best Regards, nystflame
  11. Arty with custom IP

    I have Arty A7-35T and I tried following this tutorial (http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html) to have the Microblaze communicate with custom VHDL. In the C++ file the macro for 'XPAR_MY_MULTIPLIER_0_S00_AXI_BASEADDR' matches what the address editor says. I always 0 from the address that should be the result of the multiplier. I don't know what I'm doing wrong or if anything from the tutorial needs to be done different for the Microblaze.
  12. Hello All, Have been attempting to enable interrupts on a project using the Arty and was running into issues with the intc_SelfTest failing. I loaded the Arty BSD from github thinking I had some issue with the project itself but am getting the same exact result. Any suggestions as to what I may need to change? I changed nothing in the BSD so I'm assuming it should be correct. Also followed multiple online tutorials and have been unable to solve the issue. All suggestions are greatly appreciated. Thx!
  13. No Compatible Board Interface

    Hi, I am using Vivado 2017.2 to create a project that uses a MicroBlaze soft CPU core system for a Zybo development board. The intended hardware design will be enough to be able to create a simple hello world program using the SDK. There will be UART and evuntually some GPIO to interface with the boards LEDs and switches etc. I start by adding a MicroBlaze IP to a blank block diagram. Then I run Block Automation and accept the default settings. In the TCL console I get the following info message. INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI What does this mean and do I need to do anything to correct this? Any help would be appreciated. Regards FarmerJo
  14. Arty XADC external voltage input

    Hello, I am using the microblaze system with the xadc on an Arty board. I'm able to successfully read the internal voltages and temperatures of the chip, and I made some external pins (such as the VP/VN and Vauxp0 and Vauxn0). The pins which are external have been connected in a constraints file. My power supply positive terminal is hooked into the A0 port on my arty board, and the negative terminal is hooked into a gnd port. The XADC is attached to the AXI lite bus, controlled by the microblaze. Please let me know if any of this is unclear. P.S. I've looked into the spec sheets but am still a beginner so I'm not always successful finding the right information. Greatly appreciate the help! Nystflame
  15. Hi, Is there a good example to establish communication between Zynq and Microblaze processor on Zybo? I am looking to understand how to get both these processors to talk to each other, share data etc. I'm aware of this Xilinx app note: https://www.xilinx.com/support/documentation/application_notes/xapp1093-amp-bare-metal-microblaze.pdf But i'm looking for something simpler and on Zybo. Thanks.
  16. Arty Microblaze SPI J6 Header

    Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design. I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers). Regards, Nystflame
  17. Multiple UARTLite Instantiation w/ Microblaze

    Trying to instantiate multiple UARTLite cores in a microblaze design using an Arty Board. For some reason, the output of both UARTLite modules is going through the same USB UART port as opposed to the second port I've configured. Any suggestions? [CONSTRAINTS] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_rxd] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN U11 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN V16 [get_ports usb_uart_bc127_rxd] [SOURCE CODE] #include "xparameters.h" #include "xstatus.h" #include "xuartlite.h" #include "xil_printf.h" /************************** Constant Definitions *****************************/ #define UARTLITE_DEVICE_ID_0 XPAR_UARTLITE_0_DEVICE_ID #define UARTLITE_DEVICE_ID_1 XPAR_UARTLITE_1_DEVICE_ID #define TEST_BUFFER_SIZE 16 int UartLitePolledExample(u16 DeviceId); /************************** Variable Definitions *****************************/ XUartLite UartLite_0; /* Instance of the UartLite Device */ XUartLite UartLite_1; /* Instance of the UartLite Device */ /* * The following buffers are used in this example to send and receive data * with the UartLite. */ u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ int main(void) { int Status; /* * Run the UartLite polled example, specify the Device ID that is * generated in xparameters.h */ Status = XUartLite_Initialize(&UartLite_0, UARTLITE_DEVICE_ID_0); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } Status = XUartLite_Initialize(&UartLite_1, UARTLITE_DEVICE_ID_1); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran Uartlite polled Example\r\n"); //XUartLite_Send(&UartLite_0, SendBuffer, TEST_BUFFER_SIZE); int temp = 80000; int simplecounter = 0; char links[] = "DIGILENT DIGILENT\n\0"; char linksx[] = "ARTY ARTY ARTY ARTY\n\0"; while (1) { if (1) { xil_printf("Cha Cha Cha.... %d\r\n", simplecounter++); XUartLite_Send(&UartLite_0, &links, TEST_BUFFER_SIZE); XUartLite_Send(&UartLite_1, &linksx, TEST_BUFFER_SIZE); temp = 80000; } } return XST_SUCCESS; } [XPARAMETERS] /* Definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0 #define XPAR_AXI_UARTLITE_0_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8 /* Definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_AXI_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_AXI_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_AXI_UARTLITE_1_DEVICE_ID 1 #define XPAR_AXI_UARTLITE_1_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_1_USE_PARITY 0 #define XPAR_AXI_UARTLITE_1_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_1_DATA_BITS 8 /******************************************************************/ /* Canonical definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID #define XPAR_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_UARTLITE_0_BAUDRATE 9600 #define XPAR_UARTLITE_0_USE_PARITY 0 #define XPAR_UARTLITE_0_ODD_PARITY 0 #define XPAR_UARTLITE_0_DATA_BITS 8 /* Canonical definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_UARTLITE_1_DEVICE_ID XPAR_AXI_UARTLITE_1_DEVICE_ID #define XPAR_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_UARTLITE_1_BAUDRATE 9600 #define XPAR_UARTLITE_1_USE_PARITY 0 #define XPAR_UARTLITE_1_ODD_PARITY 0 #define XPAR_UARTLITE_1_DATA_BITS 8
  18. Running XAPP1093 on Zybo

    I am trying to run something akin to the Xilinx 1093 profile. I want to have bare-metal apllications on both the ARM A9 and the Microblaze co-processor. In the SDK, I created a Zynq FSBL and three separate simple Hello World application projects, for CPU0, CPU1 and Microblaze. When I debug the application, I download all three of these projects to the FPGA. But I only see a Hello World from Microblaze and CPU1 on the terminal. If I don't download the CPU1 project, then I can see the Microblaze and CPU0 Hello Worlds just fine. I have attached the tcl script for the block design I used. As far as the application projects, they are the simple auto-generated hello world .c files from the SDK. What prevents CPU0 from sending Hello World to the terminal when the project for CPU1 is also downloaded? My end goal is to run either an image processing or an encryption algorithm, that divides tasks between the two cores and Microblaze or the ARM processor in general and Microblaze. 1) Should something change or be added to the block design for this to happen? 2) Is the communication between ARM and MB achieved through functions in the .c files? design_1.tcl
  19. Memory issues in Arty-7x Microblaze

    I'm working on some embedded software on the Arty board and programming in Microblaze. When I try to allocate an array of sixteen-bit numbers, length 512, it works just fine, but the same array set to length 1024 causes malloc to return NULL. After some experimentation and testing, I believe this is because the Microblaze processor has run out of internal memory. However, the Arty board is supposed to have 256MB of DDR memory. An interface to the memory already existed in my block diagram (copied from Getting Started With Microblaze with some PMods added), so I assumed that the DDR memory was already being used by the Microblaze processor, but 256 MB of memory shouldn't be struggling to deal with a 2KB array. (Outside of the allocated array, the program is very small.) Is there something special I need to be doing to access the DDR memory from inside Microblaze?
  20. How to add own logic to Arty board flow?

    The Arty board examples and tutorials use the Vidado drag and drop editor. But, there is no example how one would add their own custom logic. I have hacked this so far by dropping a peripheral and then replacing the stub verilog file, but it would help to show how this should be done. The natural would be to drop in a custom bus i/f file (e.g. using the AXI to AHB or AXI to APB bridge to a stub) and also how you add pins to the port list. Hacking away at it seems just wrong - if there is some intended flow, it is not apparent. The old way of editing the .ucf file and adding the ports to the top file does not seem like a fit for this SDK/Microblaze environment. Thanks, Paul
  21. clock mismatch in IP integrator

    HI there, I have a simple HLS design which I exported as an IP Core to implement on my target. But I get the following error when I go ahead interconnecting the IP cores. Does anyone have any idea as to how I can work around this obstacle? I even tried changing the frequency of the ports, but the fields are inactive. [BD 41-237] Bus Interface property FREQ_HZ does not match between /matrixmul_0/INPUT_STREAM(100000000) and /axi_dma_0/M_AXIS_MM2S(200000000) [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_dma_0/S_AXIS_S2MM(200000000) and /matrixmul_0/OUTPUT_STREAM(100000000)
  22. Hello all, I wish to receive 10 Mb of data through Ethernet using TCPIP protocol. I am newbie to LWIP so use Microblaze server demo code for reference. The problem i faced is i only able to receive 1460 bytes of data with echo server example code. I also added pbuf_copy_partial() function and specified pointer where data should be store but when i try to read data from pointer specified i am getting some garbage values. i also acknowledge packet reception but still i would't able to fix issue. i have also attach snapshot of code which i modified please suggest steps for data reception. Regards, Kumarkk
  23. I've done quite a bit of work with using the Cortex A9 on the Zeboard, and as such am at home in the tools flow. I also have a Nexys4 DDR, and need a processor for a project I'm working on...so I figured I'd give the Microblaze a whirl. I did the Hello World tutorial that is on the Digilent site...pretty straightforward, except for one strange bit of behavior: When I run my hello world app, main runs twice, both in debug and release mode. I stepped through the code, and it appears that somewhere in cleanup_platform(), main gets invoked again (recursively). This ends up running init_platform() again, as well as printing my message to the screen twice. I am going to see if I can track down where in cleanup_platform() this is happening, but was wondering if somebody else has seen this, and can offer an explanation and/or fix? My design is completely according to the tutorial right now...I haven't added any of my own HW logic or additional SW code yet. UPDATE: I did some further debugging, and it looks like this happens during the call to Xil_ICacheInvalidate() (xil_cache.c). Getting more specific is difficult as it appears to happen some time during the loop in microblaze_invalidate_icache.S line 70. I'm no expert with the MB ISA yet, but can certainly deduce that this is walking each cache line, and I'm assuming, marking them as invalid. While doing this debugging, I actually got the processor into a state where this recursive call into main would continue as long as I'd let it, each time, printing out a new message. Very strange. Thanks, Dave
  24. Hi, I have a simple design. In an ARTY board, I need to read from ddr3 initialized in SDK and write to pmod constantly in a loop. What is the recommended way to do this? Do I need to use the DMA? Is there a reference design for ARTY board? Thanks
  25. Hi Mr./Ms., I have successfully make Nexys Video Microblaze server example works following: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start However, the echo server only works under standalone OS but not xilkernel OS. It gives me the error "unable to alloc pbuf in recv_handler" called from "setup_rx_bds" function, even I haven't telnet the server yet. I have tried: 1. increase heap size 2. increase pbuf_pool_buffer size, pbuf_pool_size 3. increase mem_size, mem_n_pbuf 4. enable jumbo frame 5. increase TX and RX buffer size in axi_ethernet component in vivado The enlarged men size can delay the appearance of this error, but error message still come out and I cannot echo successfully. I guess it is not a pure problem from memory size since standalone works, maybe because the xilkernel is too busy so that cannot catch up with the speed of coming packets. So far the speed of LINKSPEED is also 100MHz as well as sys frequency. I wonder any way can slow down the coming packets ? PS: board is Nexys video, vivado is 16.2, xilkernel is 6.3, lwip is 1.4.1 Thank you very much!