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I'm a newbie here and I’m working on a inverter test bench project where I have two three-phase inverters connected through an inductive load. The idea is to emulate in real time the behave of an electrical machine. To be clearer, the first inverter is going to be tested (Device Under Test) and the second one plus the inductive load must behave like an electrical machine. To do so, we are going to use a FPGA board, which must have the following specifications: - Capable to drive both inverters switching at 50kHz (each inverter has 6 MOSFETs switching at this frequency) - 20 digital I/O - 4 ADC with 16 bits (ideally) and 20MHz at least. The ADCs can be integrated or not in the FPGA board - Capable to communicate in real time with Matlab/Simulink - The board will be placed inside the test bench, in a temperature around 50°C We know that we are going to use Vivado to the VHDL coding, but we are not sure about the ADCs, regarding the Eclypse Z7 with the two Zmod ADCs. We want to code the least possible in VHDL (no VHDL coding if possible), so my questions are: 1) Are we going to have to code the ADC data acquisition? 2) Is the VHDL code generation done automatically by Matlab? I do have the toolbox for HDL coding. Our budget is around €1000,00. I would like to know if the board Eclypse Z7 with the two Zmod ADCs is a good choice for the application and if you have another advices it would be highly appreciated. I hope I made myself clear. Thank you!
Hello everyone! I'm Harri, an EE Master's student. Me and my team are currently working on assignments for three different courses around the topics of FreeRTOS, digital filtering and hardware-in-the-loop with MATLAB and Simulink. We are using the Zybo Z7-10 board and Vivado/SDK v.2018.2. In the first project, we are trying to use the Xilinx port of FreeRTOS to run a control engineering state-space-model on the ARM side. The vision is to have the model, which is a DC-converter, run at 10 kHz and the output of the model is shown as PWM to the onboard RGB LED. The project should also have a menu system via UART/Ethernet or by buttons and switches. These should be mutually exclusive, so when one input method is in use, the other will be blocked. We are kind of puzzled with this one, because our initial plan was to enable interrupts for GPIO and UART and then have those either take a semaphore from the ISR or send a struct to a queue from ISR. So far using the xscugic and registering the interrupts has been a huge puzzle for us and the workflow around this is unclear to us. We have managed to get task notifications to work from button press to periodic task, but trying anything more than that e.g. queues seems to not work. Any help on these topics would be highly appreciated! The other two project are on digital filtering. We are simply trying to run some simple audio effects on the music from LINE/MIC IN -> OUR FILTER -> HPHOUT. We have used this example https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-dma-audio-demo/start as a starting point and got that to work. Now we would like to remove the DMA part and just add our filtering IP in the middle. The PS side and buttons would be used for simple visuals for amplitude on LEDs or enable/disable certain effects inside the block. Any guidance on this one? We have already read the audio codec manual/register map, but we are missing something. Also, if someone has experience with Mathworks MATLAB and Simulink and this Zybo Z7-10 board, that would be awesome, as the other project is actually more focused on the filter design part and not FPGA stuff. Also, our professor would be glad to have this kind of HIL setup demoed: https://se.mathworks.com/help/hdlcoder/examples/running-an-audio-filter-on-live-audio-input-using-a-zynq-board.html. We have tried following the setup guide for that one, but we are tripping at the point of connecting to the board and running the simulation. The SD card setup also is not well explained. I'm hoping to get help, ideas and inspiration from here! I'll be glad to also share the projects when they're done. Cheers, Harri
I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module. Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board? Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board? Thanks, Shruthi Sampathkumar.