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I'm a newbie here and I’m working on a inverter test bench project where I have two three-phase inverters connected through an inductive load. The idea is to emulate in real time the behave of an electrical machine. To be clearer, the first inverter is going to be tested (Device Under Test) and the second one plus the inductive load must behave like an electrical machine. To do so, we are going to use a FPGA board, which must have the following specifications: - Capable to drive both inverters switching at 50kHz (each inverter has 6 MOSFETs switching at this frequency) - 20 digital I
Hello everyone! I'm Harri, an EE Master's student. Me and my team are currently working on assignments for three different courses around the topics of FreeRTOS, digital filtering and hardware-in-the-loop with MATLAB and Simulink. We are using the Zybo Z7-10 board and Vivado/SDK v.2018.2. In the first project, we are trying to use the Xilinx port of FreeRTOS to run a control engineering state-space-model on the ARM side. The vision is to have the model, which is a DC-converter, run at 10 kHz and the output of the model is shown as PWM to the onboard RGB LED. The project should
I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module. Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board? Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board? Thanks, Shruthi Sampathkumar.