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Found 11 results

  1. Hi folks, I hope all is well with you. I am a newbie to zynq AP SoC. I started working with Digilent Zybo board, lwip ethernet echo server example. Problems facing. 1. Auto Negotiation failure if i set the link speed to auto in bsp. If i set link speed to 1000Mbps the program says that the ethernet link is down. 2. How to modify the echo server program where i can send and receive data to a specific ip address with specific port number as Server and also as client. I am using a Xilinx SDK version 2018.3 Operating system: Windows 10 Happy to hear a best possible solution from you folks. Thanks in advance. Regards Ajeeth kumar
  2. Hi Mr./Ms., I have successfully make Nexys Video Microblaze server example works following: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start However, the echo server only works under standalone OS but not xilkernel OS. It gives me the error "unable to alloc pbuf in recv_handler" called from "setup_rx_bds" function, even I haven't telnet the server yet. I have tried: 1. increase heap size 2. increase pbuf_pool_buffer size, pbuf_pool_size 3. increase mem_size, mem_n_pbuf 4. enable jumbo frame 5. increase TX and RX buffer size in axi_ethernet component in vivado The enlarged men size can delay the appearance of this error, but error message still come out and I cannot echo successfully. I guess it is not a pure problem from memory size since standalone works, maybe because the xilkernel is too busy so that cannot catch up with the speed of coming packets. So far the speed of LINKSPEED is also 100MHz as well as sys frequency. I wonder any way can slow down the coming packets ? PS: board is Nexys video, vivado is 16.2, xilkernel is 6.3, lwip is 1.4.1 Thank you very much!
  3. Hi all, I am reposting here an issue previously published on the Xilinx forum https://forums.xilinx.com/t5/OpenAMP/Zynq-AMP-CPU1-baremetal-access-to-gem0/m-p/827569#M418 still without a solution. I repeated the test on PicoZed 7015 board and on the Zybo as well. My system configuration is as follows: Vivado 2016.3 on a Linux Debian host Standard Zynq design over Zybo (just use ethernet and the ps7_uart) CPU0 -> baremetal "Hello World" application CPU1 -> baremetal "lwIP echo server" with lwIP library to use gem0 CPU0 is run as master CPU (and launching the ps7_init methods), while CPU1 is started later with USE_AMP flag activated. Goal: To have the CPU1 accessing the Ethernet with LwIP and keeping the CPU0 available for other tasks (most probable, it will run Linux later on). Issue: Whenever the USE_AMP flag is turned on on CPU1, the "LwIP echo server" did not send packages over Ethernet (verified with Wireshark) neither answer back to ping. In the other case, when USE_AMP is deactivated, the Ethernet works as expected yet CPU0 stops working (due to the SCU contention)... Have somebody face the same issue? In the attachment, you might find the reference project, with CPU0/CPU1 example application (from the XSDK template). Thank you, Luca proj_reference_Zybo.zip
  4. Hi, I am trying to run the lwIP echo server application project template from the Xilinx SDK on my PYNQ board. I have followed this tutorial for the Zybo FPGA board (which also contains the ZYNQ): https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start Everything works fine until the very last step, when I come to connect to the echo server using telnet. The PYNQ is telling my via serial comms that Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 So I followed the instructions in the above link to set up the ethernet connection on my Windows PC with the static IP address 192.168.1.11 using the given netmask. Unfortunately when I come to connect via telnet using Putty, it tells me that the host is unreachable. I have also tried using my Ubuntu PC but I get the same problem. I have tried debugging the echo server in the Xilinx SDK by setting a break point in the recv_callback() function, but it never seems to reach that part of the code, indicating that no packets are ever received from my PC. Does anybody have any idea what I could be doing wrong please? Thanks!
  5. Does anyone have the project for the initial project containing all peripheral interfacing?
  6. Hello All, I'm having trouble running the Ethernet echo server on my pynq board barebones. I realize that the phy is different than what the example targets, so I changed the link rate in the bsp to fixed 100Mbits and did the same on my PC driver side. Unfortunately this didn't solve the problem and telnet still gives an unable to connect when I try 192.168.1.10 7. I'm wondering if maybe it is a board files problem? I am using the files for the Arty Z7 -20, which I thought would be close enough, but maybe some of the Ethernet stuff is wired a little differently?
  7. Hello, I have created a TCP server on Xilinx Zynq 7000 Zedboard and TCP client on MATLAB on host computer. Zedboard and the host computer are connected through the Ethernet. The client requests the connection to the server, SYN, SYNACK and ACK packets are delivered successfully and the connection is established. (Packets are monitored on wireshark on the host computer). Now, If the client keeps sending the data continuously to the server, then server receives the data and process them. BUT the server crashes if I take some time interval in sending the data. For example: If I send data from client to server at time 0, and I take a gap of 60 seconds and then try to send the data from client to server, then by this time the TCP server has crashed and it does not receive data.If I keep sending data continuously then it does not crash, but if I take some time sending the next data, then TCP crashes. can anyone suggest where I am going wrong I have been looking over the Internet to find solutions but any help/suggestions would be appreciated.Thanks
  8. Hello all, I wish to receive 10 Mb of data through Ethernet using TCPIP protocol. I am newbie to LWIP so use Microblaze server demo code for reference. The problem i faced is i only able to receive 1460 bytes of data with echo server example code. I also added pbuf_copy_partial() function and specified pointer where data should be store but when i try to read data from pointer specified i am getting some garbage values. i also acknowledge packet reception but still i would't able to fix issue. i have also attach snapshot of code which i modified please suggest steps for data reception. Regards, Kumarkk
  9. Hi, I am using ethernet of Zybo,and want to utilize lwip to realize tcp,however,how can I obtain the data reveived from raw api and save it in BRAM or distribute ram? Regards, Sophia
  10. Greetings, I'm developing TCP application based on the LWIP RAW and I'm stucked with a strange behaviour with similar hdl design and same application code on two different hw platforms - the trainer board Nexys 4 DDR and evaluation board Xilinx VC707 My problem is that everything works on VC707 board (for now). My application code is a TCP server what sends continually data to connected client. I was testing this code thoroughly so it handles every possible situations (reset, abort flags, unplugged cable, connecting more clients...), dumping LWIP stats to check if there are some memory leaks and another stuff. I left this board to do its job for couple of hours/days without a problem. It just lives like I want. The HDL design is simplified reference design for VC707 (Microblaze, DMA, AXI Ethernet...). The softprocessor is set for best performance (optional settings for instructions, cache and stuff). I'm sharing VC707 with another colleague so sometimes I continue with the development on "slower" board Nexys 4 DDR. HDL design is the same like here https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start So only difference is ethernet part - Axi EthernetLite and MII to RMII cores. VC707 has the gigabit ethernet. The problem is that I'm getting drastic slowdown of throughput over time of usage. First I'm getting stable 22 Mbit/s, then after some time bandwidth fluctuate down and up and then finally it gets down to crappy speed. I can't even see it in the jpetf utility (GUI version of iperf) - sometimes it make peak to full bandwidth for a few seconds then it fall back to like 100 kBit/s. I don't see anything suspicious in Wireshark log or in LWIP stats display either. It just runs slow. As I said...this code works fine on VC707 board so I suspect there is maybe something work with Axi EthernetLite/MII to RMII cores. There are some critical warnings in implemented design: [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN2.RER_FF'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN2.TEN_FF'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[1].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[1].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[2].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[2].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[3].RX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. [Place 30-73] Invalid constraint on register 'design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[3].TX_FF_I'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. Is it possible source of the problem. How can I fix it? Just saying I'm pure embedded C developer...I have made this design with help of your tutorials/reference stuff. I would like to get some advice or get kicked to right direction in finding source of problem. Is possible to get some information about ethernet driver from LWIP? Is possible reset these IP cores from Microblaze? Thanks and Regards Daniel
  11. Hi I want to utilize sdk to test echo server lwip,fpga program and run configration are done.However,in console,there are some lines make me confused. -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back link speed: 1000 DHCP Timeout Configuring default IP of 192.168.1.10 Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 When I ping the board on PC,it displays "can't access the destination host" My board is Zybo.The hardware been built in vivado 2014.3.1 is a Zynq7 System Processing Core.What makes wrongs? Regards, Sophia