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Found 14 results

  1. PTSmith

    CMOD A7 100 MHz clock in

    So, I want to bring in a 100 MHz clock and route it to a CMT to generate a bunch of lower frequency clocks all phase-locked to the 100 MHz. I appreciate I can't output an LVDS signal, but it looks like I should be able to bring in an LVDS signal as long as I supply my own 100 ohm termination to pins 18 and 19 for example. Am I missing anything? Paul Smith Indiana University Physics
  2. I am seeking an FPGA-based solution to communicate with a commercial display driver via mini-LVDS, which is a unidirectional interface specification established by Texas Instruments. From my understanding of the Artix-7 documentation, transmitting mini-LVDS signals is possible by exercising the MINI_LVDS_25 I/O standard on any HR I/O bank, so long as the desired bank VCCO = 2.5V. I possess an Arty S7 board, which appears to have high-speed JA and JB PMOD ports for high-speed protocols such as LVDS. However, Vcco for bank voltages 0, 14, and 15 are set to 3.3V, but both mini-LVDS and LVDS mandate 2.5V rail voltage in 7Series devices. Is it possible to alter the feedback resistor network for FB1 (shown on pg. 10 of to convert Vcco 3.3V to 2.5V? I believe by reducing R200 from 31.6K to 21.5K, 2.5V output from channel 1 of ADP5052 is achievable. Please confirm that there are no unintended consequences here. Also, I worry about signal integrity when routing differential pairs through standard 0.1" pin headers. Is this a valid concern for my frequencies of interest (50 ~ 200MHz)? I appreciate your input.
  3. Alberto Vigato

    LVDS in CMOD S7

    I'm using a CMOD S7 board and I intend to use a couple of LVDS output pairs. I set the output pairs in Vivado as LVDS_25* and it is regularly synthesized. But I don't see any output on those pairs, and it is probably due to the power supply to the FPGA bank involved. My question is: can I use this kind of LVDS output on this evaluation board?
  4. Hi there! I'm trying to make differential clock(100MHz from oscillator) to differential clock output(40MHz differential) clk_100M_P&M is connected to external crystal oscillator(input) and I allocated clk_40_P&M to PIO port(output). clk_front , clk_back is for check point. when I checked, the result was : clk_front : 100MHz & clk_back : 40MHz . However, clk_40_P &N port didn't output some waveform. I have no idea what's the problem. 1st trial : clk_front & back : LVCmos33 and clk_40_P & N : LVDS25 -> result : LVCmos33,(bank34) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) 2nd trial : clk_front & back : LVCmos25 and clk_40_P & N : LVDS25 -> result : LVCmos25 ,(bank35) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) thank you for your help!
  5. Hello, I am trying to implement LVDS (1.2V nominal) using the Digilent Arty-S7 25 board. The schematic shows that the JA and JB Pmod connectors have 4 diff. pairs per connector. However, it looks like VCCO (the power supply for this I/O bank) is tied to 3.3V. To my knowledge, there is no differential I/O protocol that uses 3.3V. Does this mean that JA and JB can't be used for differential pairs? (Wouldn't that negate the point of running the differential pairs in the first place?) Or do the pins just output the correct voltage when you implement the LVDS protocol? Please help! Thank you
  6. Hi! In previous topic i have asked about first start with Zynq core (i have Ettus E310 board) Now it is time for connecting ADC that is on board AD9361 . I want to get some signal and receive it via ADC - i do not understand how to connect ADC (how to edit Zynq for getting data via RF board connector (via LVDS??) I have read manual (p.34) about that ADC I hope, somebody help me to edit blocks or code in Vivado and get digitalized data from ADC. Best regards.
  7. chm

    A7-35T LVDS pins

    Hello there, we are trying to use the A7-35T in an LVDS application, but it seems that the pin assignment on the DIL is not optimized for that, the differential pairs are in general not located close to each other. Does anyone have a PCB printout so that we could choose those LVDS pins (we need only two pairs) that are the least badly routed? Any experiences perhaps? thanks christian.
  8. Hi, PRBS data from 1st board--> LVDS out (data)--> LVDS in (data)--->2nd board-> Aurora Tx (2nd board)-> Aurora Rx (1st board). Almost, i have completed the first part (1st board side), but in second part i dont know how to connect the IBUFDS(LVDS in) with microblaze and FIFO setup. Because IBUDS does not have AXI kind of connections. Please anyone guide ma.
  9. In the Nexys Video Artix 7 board the FMC connector contains 34 differential pairs connected to the FPGA. Can I use two tracks of a differential pair as two single ended CMOS signals. Also can I configure LVDS pins and CMOS pins on a single I/O bank of the FPGA?
  10. Hi, I'm kind of new to using external I/O connections on FPGA boards but I'm tasked with a project where I plan to interface a high-speed camera with 6 lvds pairs (4 data + 1 clock + 1 sync) with the clock input reaching up to 360 MHz, translating to a max data flow of 720Mbps through each of the 4 data pairs. Although this is the optimal operating condition, I don't necessarily have to achieve such speeds if I can get something close to that using an inexpensive board as low-cost is an important factor here. I was told to look at the following xilinx fpga boards with the Zynq 7000 series chips: Zybo (~$200): 512 GB DDR3, has VGA and HDMI, only pmod I/O connectors. From what I've read, I understand the high speed pmods are set to 3.3V, but can work at a lower voltage if only used for input, but do I need to physically alter the board for this? What speeds can I actually reach through these connectors? MicroZed (~$200): 1 GB DDR3, no display out, will have to connect through microheaders on the back, but I can control the I/O bank voltages through the inputs from my carrier card for LVDS. MicroZed manual says "Differential LVDS pairs on a -1 speed grade device are capable of 950Mbps of DDR data" but does this mean the microheader connector is also capable of this rate? I ask this because a similar board from MYiR, the Z-turn (~$100), is very similar in design (but includes HDMI and surprisingly much cheaper) and their support says "Z-turn Board expansion connectors are most for PL ports which can support LVDS differential input, the speed is up to 200MHz in theory." which seems too slow. From what I've gathered, the Z7010/20 chips and the DDR3 ram are very capable of handling the speeds necessary for operating the camera sensor and the large ram size is important for storing the large number of frames, but I'm confused whether the board these are on allows these chips to receive the input fast enough to make full use of both these chips and the camera sensor. Are there any other low-end boards with large enough memory and fast I/O that can make full use of this camera sensor? Any help or guidance is much appreciated on where to look and how to design. Thanks.
  11. Hello! I use Nexys Video board and plan to use a Pmod connector with LVDS standard (input and output). Following the reference manual, the only Pmod connector that provides LVDS (LVDS_25) for input and outputs is JXADC (with V_ADJ=2.5V). This connector is equipped with 100 ohm series resistors. The Xilinx documentation UG471 (v1.8, pages 91-93) does not describe that series resistors are recommended or required. Is it possible to use Pmod connector JXADC for LVDS inputs and outputs with that board? Or must I short cut the series resistors (R42-R45/R47-R50)? Many thanks in advance!
  12. I am wondering if, specifically for the Arty Artix-7, one of the pmod ports could theoretically be configured to carry enough data to drive a 1024x600x18-bit LCD at 24fps or greater, preferably on an LVDS interface.
  13. I'm new to FPGAs and the zynq. I'm interested in a zybo board and would like to know how to put an lvds output on the logic part of the zynq and how to get this connected to a framebuffer device I can use in linux to output graphics to?
  14. Greetings, I need to know what is the output characteristic impedance of the VHDC connectors on the Genesys Virtex 5 FPGA Develpment Board. The datasheet only says they are impedance-controlled matched pairs and the schematic does not have this info. Some online forums said SCSI is defined by ANSI X3.13, the nominal diff cable impedance is 122 Ohms and I want to check if my board IO is consistent with this standard or not. I need to design a mating board to convert high speed differential signals into single ended, and signal integrity is a big deal. Thanks in advance, Emanuel