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Found 11 results

  1. Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs and outputs and see how the timing diagram behaves and try to implement the logic based off of that? Or should I be first be treating this as a "state machine" and draw a systematic schematic of showing all the inputs and outputs, showing when they should go HIGH or LOW at their certain times? Are timing diagrams usually implemented in a state machine logical flow? Was hoping to gain some knowledge and understanding from the people who are experienced writing Verilog logic based off of timing diagrams and was hoping to see your systematic approach of how it should be implemented as if I was an engineer. Thank You.
  2. mgssnr

    SPI under Logic

    Hello, I just received my AD2, and I really like it! I like the WG and the scope, and while it took me a little while to figure out the Protocol analyzer, it does a pretty good job showing the data. However, at first glance, the SPI protocol handler under the logic analyzer is somewhat limited because it only handles one channel. One could capture four signals by using the logic analyzer and doing the work manually, but I would like to be able to handle all four (or 6) SPI channels in the logic analyzer, too. I have an MCP3208 which requires a command in the first 10 bits, and then in the next 14 bits returns the data on the MISO pin. Is there any way to do this in the logic analyzer? Thanks Matt Gessner
  3. Hi, I am new to the Digital Discovery I am capturing data with the SDK and would like to get the data of each individual DIN pin separately instead of together in the same buffer. My setup: Signals coming in from DIN0 and DIN2. Code is given below. What I would like to do is add DIN3 as clk and get the data for that signal in a separate buffer. Currently the data for both signals comes in as combined and I have not been able to find a way to capture it separately in the SDK. This can however be done with Waveforms2015 and I am trying to mimic that. If I have to use a DIO as clk input, that would be fine too. hzSys = c_double() dwf.FDwfDigitalOutInternalClockInfo(hdwf, byref(hzSys)) divider_value = c_uint(int(hzSys.value/1e3)) pin_24_value = createdatavalue([0x01,0x03,0x07,0x0f,0x1f,0x3f,0x7f]) dwf.FDwfDigitalOutEnableSet(hdwf, c_int(0), c_int(1)) dwf.FDwfDigitalOutTypeSet(hdwf, c_int(0), DwfDigitalOutTypeCustom) dwf.FDwfDigitalOutDividerSet(hdwf, c_int(0), divider_value) dwf.FDwfDigitalOutDataSet(hdwf, c_int(0), byref(pin_24_value), 8*7) #pin_25_value = createdatavalue([0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa]) pin_25_value = createdatavalue([0x00,0x00,0x00,0xff,0xff,0xff,0xff]) dwf.FDwfDigitalOutEnableSet(hdwf, c_int(1), c_int(1)) dwf.FDwfDigitalOutTypeSet(hdwf, c_int(1), DwfDigitalOutTypeCustom) dwf.FDwfDigitalOutDividerSet(hdwf, c_int(1), divider_value) dwf.FDwfDigitalOutDataSet(hdwf, c_int(1), byref(pin_25_value), 8*7) dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) sts = c_byte() dwf.FDwfDigitalInDividerSet(hdwf, c_int(10000)) dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(16)) nSamples = 8000 rgwSamples = (c_uint16*nSamples)() dwf.FDwfDigitalInBufferSizeSet(hdwf, c_int(nSamples)) dwf.FDwfDigitalInTriggerSourceSet(hdwf, c_ubyte(3)) # trigsrcDetectorDigitalIn dwf.FDwfDigitalInTriggerPositionSet(hdwf, c_int(nSamples)) dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(1<<1), c_int(0)) # DIO2 rising edge dwf.FDwfDigitalInAcquisitionModeSet(hdwf, acqmodeRecord) dwf.FDwfDigitalInConfigure(hdwf, c_bool(0), c_bool(1)) print (" waiting to finish") cAvailable = c_int() cLost = c_int() cCorrupted = c_int() cSamples = 0 fLost = 0 fCorrupted = 0 while cSamples < nSamples: dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts)) if cSamples == 0 and (sts == DwfStateConfig or sts == DwfStatePrefill or sts == DwfStateArmed) : # acquisition not yet started. continue dwf.FDwfDigitalInStatusRecord(hdwf, byref(cAvailable), byref(cLost), byref(cCorrupted)) cSamples += cLost.value if cLost.value : fLost = 1 if cCorrupted.value : fCorrupted = 1 if cAvailable.value==0 : continue if cSamples+cAvailable.value > nSamples : cAvailable = c_int(nSamples-cSamples) # get samples dwf.FDwfDigitalInStatusData(hdwf, byref(rgwSamples, 2*cSamples), c_int(2*cAvailable.value)) cSamples += cAvailable.value print ("Acquisition finished") dwf.FDwfDeviceCloseAll() print ("Recording finished") if fLost: print ("Samples were lost! Reduce sample rate") if cCorrupted: print ("Samples could be corrupted! Reduce sample rate") f = open("record.csv", "w") for v in rgwSamples: f.write("%s\n" % v) f.close()
  4. Just recorded some logic data using my new Analog Discovery 2 on my Mac. Now I want to zoom in and look at the data. According to the tutorial there is suppose to be a "hot track" button that lets you zoom in but I don't see any such feature. So how do you zoom in? I attached a screenshot if it helps.
  5. Hello, I think the latest waveforms software is fantastic. However, I still have a problem with triggering, specifically protocol triggering. In the enclosed screenshot, I have a UART and OneWire and a SPI protocol decoder. If I choose Simple triggering, everything is ok, but if I choose Protocol-UART-TX-GPIO1 (UART decoder form the Protocol selection button pull down menu) then the OneWire and SPI decoders trigger-selection-arrows switch too! What I would like is that I can only choose the UART OR only the OneWire OR only the SPI decoder as suggested by te Protocol selection button pull-down menu. So I can see where I am triggering on. Am I right? or is what I ask impossible? Thanks in advance, Hans.
  6. HansV

    UART triggering

    Hi, In the attached picture i try to trigger in 2 way's 1. Protocol on value: h48[H] 2. Direct on the Falling edge Both ways don't work the system randomly triggers on what? Thanks in advance, Hans.
  7. Hi, I noticed a strange behavior in the Logic tool, if i "Save" this workspace (notice Position: 475,6 us, Base: 116 us), And i save, close and open that same workspace again , i got this result; (notice Position: 472 us, Base: 236 us) Ik know its not a major / big problem i only try to improve things. Thanks in advance, Hans
  8. Hi, Whenever I am trying to use the logic analyzer in the 4th mode (16 x 16k buffer) and trying to capture spi events, the software get stuck to "config" as you can see on the picture attached. Please help!
  9. HansV

    Logic buffer tabs

    Hi, I try to use the buffer tabs in the logic application for different acquisitions. example; acquisition2 (Tab 1-timebase 61 us/div) temperature registers (in this case). acquisition3 (Tab 2-timebase 376 us/div) all registers overview. But if i make acquisition 2 with a timebase of 61 us/div and make a new Tab (+button) for acquisition 3 (376 us/div) and make a Single shot, the program changes the timebase in my previous made Tab 2, too. What is the use of these Tabs if this is the case? Thanks in advance, Hans.
  10. Capnfrost

    Basic Logic Function Help

    Hello all, I am trying to program a Basys3 to perform basic logic functions. It seems like it would be really easy to accomplish but I am still a little unclear how to program the board as well as write for Vivado. For example I think that I should be able to, in theory, program the board to be an AND gate by writing a program that looks at switch 0, switch 1, and LED 0. If switch 0 and switch 1 are both switched on LED 1 comes on. It sounds super easy I just have no idea how to write in vivado. Any help would be super appreciated. Thanks Capnfrost
  11. Are there any plans to add more interpreters? Can users create their own?