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Found 81 results

  1. Hi All, Is there anybody have any experience about XUP (Xilinx University Program) USB-JTAG Programmer Revision-G using with Vivado 2015 or 2018? I have some little experience with Vivado 2015.5 and 2018.1 but regarding my experiences XUP USB-JTAG Programmer is not compatible with Vivado? I tried all ways on Centos-7 OS and the particular script (install_drivers.tar.gz). I aimed to program the Zedboard for petalinux applications developing but no success with XUP USB-JTAG Rev.G and Vivado running on Centos-7. Could you please share any suggestions if you have? Regards. Kursat Gol
  2. anshumantech

    HS1 JTAG Circuit

    I want to know about the circuit diagram of HS1. Can anyone help me out with it? I searched on Digilent website too but it is currently unavailable there.
  3. I have been working on developing an I2c interface on the arty s7 board, and during one of my hardware tests, I noticed that my debug LED's had shut off. I went to resend my bit stream and noticed that my hardware manager was no longer connected to the device. Whenever I plug the device in, it is clear that I am getting power, as the done LED, the power LED, and the TX LED are all on. However, when I attempt to reset the device using either the reset or program button, no change occurs (that is, the strobing LED pattern does not commence as it has in the past). I have checked my device manager and found that the s7 is no longer connected, and have restarted my computer as well as unplugged and replugged the s7. My primary concern is that this may be a hardware issue, but I am unsure as to what I could have done to cause this. I have been running 3 3.3v pins from the arty to a teensy. Any advice would be helpful. Thanks, Micah
  4. stark

    Digilent JTAG HS2 cable not working

    Hello , I am working with Metaware IDE and the device uses Digilent HS2 JTAG cable. But there is a problem with the JTAG cable and I could not identify the issue. Kindly guide me with this. I have attached the picture of the error. Thanks
  5. Jaime_mc2

    JTAG-HS1 with breadboardable CoolRunner-II

    Hello, I'm planning on buying the product "Cmod C2: Breadboardable CoolRunner-II CPLD Module" to make some prototypes of future designs. I saw that, in order to program its CPLD (XC2C64A), I need to buy a USB to JTAG cable. Is the Diligent's JTAG-HS1 programming cable compatible with that CPLD and board?. I will be using the last version of ISE on Windows 10, will it be a problem?. If it helps answering, this are the links of the Digilent's store of those products: Breadboardable CoolRunner-II: https://store.digilentinc.com/cmod-c2-breadboardable-coolrunner-ii-cpld-module/ JTAG-HS1 programming cable: https://store.digilentinc.com/jtag-hs1-programming-cable-limited-time/
  6. I just received my JTAG-HS3 Rev A programming cable and if I plug it into my windows 10 machine I don't see anything unique showing up in the device manager. I know something is popping on and off because I can hear the device attached and device detached sounds from windows. So what should it show up as?
  7. Hello I have a Digilent USBJTAG HS2 and I'd really like to use it with TopJTAG's Probe software. The software has native support for the Digilent USB-JTAG but not the USB JTAG HS2. Having said that, it supports "custom" JTAG probes based on the FTDI chipset and recognises the HS2 as such. This is encouraging. When I select the Custom FTDI option it asks me to tell it what to do with the FTDI GPIOs and advises that different probed need their GPIOs setting up differently - often to enable buffers, drive tRST, and stuff like that. Sounds fair enough to me. The problem is that I cannot find documentation on how the GPIOs are used/configured on the HS2. The schematic would help, but the link to the schematic on the digilent website is dead. Can anyone help with the GPIO config or a schematic of the HS2? Many thanks. Andrew
  8. Mahdi

    How to split a JTAG between two pmods?

    Hello, I am using Arty-Z7-10 board with 3 Pmods (NAV, GPS and RTCC), while there are only 2 JTAG ports available on the board. So, I decided to buy one of these 2*6-pin JTAG splitter cables and divide one of my JTAG ports between PmodGPS and PmodRTCC (since both of them need only one row of JTAG). Now, I am trying to make a block design and connect both of them to one JTAG, but it does not seem to be feasible. When I connect the first Pmod to the JTAG port, it occupies the whole port and it does not allow me to add another Pmod to it. Is this something I have to do in Verilog, and modify my XDC file? or is there an easier way to do it by just dragging and dropping the IPs in the block design? Best, Mahdi
  9. chcollin

    Atlys USB JTAG problem with VirtualBox

    Hi FPGA gurus ! I am facing trouble while trying to attach my Atlys USB JTAG device to a Centos 6 virtualbox VM. I recently had no choice but to upgrade my computer from Windows 7 to Windows 10. As a Windows 10 version of ISE 14.7 was available, I decided I could do the upgrade before realizing that ISE 14.7 for Windows 10 was indeed ISE 14.7 for Linux running a VirtualBox... Nevermind. The problem is that it seems I can't attach Digilent USB JTAG to the VirtualBox. Here is my configuration : Windows 10 Pro VirtualBox 5.2.8 (I upgraded it so that I could install Extensions to enable USB 2 and USB 3 support) Adept2 is installed on Windows 10 and works fine, Atlys board is recognized and I can run the test application OK. Now, here is my problem : Let's turn on the computer first and do a fresh test ! Atlys Board is attached to USB ports (JTAG and UART) but is turned off. VirtualBox USB configuration is configured as shown in USB_parameters.jpg Now, let's turn VM on, Atlys board still off. The attachable USB device list in VB is shown in USB_devices_atlys_off.jpg As you can see, neither JTAG nor UART devices are listed, which is expected as Atlys board is off. Now, let's turn the Atlys board on and see if the listing has changed... It has ! as shown in USB_devices_atlys_on_1.jpg Also, you can see in Device_mgr.jpg that Windows has no driver problem with JTAG and UART devices. You may notice UART device is automatically attached. Looking at /dev/tty* shows that the UART device is now available through /dev/ttyACM0 as shown in TTY_devices.jpg Let's have a look at the JTAG device status (USB_devices_atlys_on_2.jpg), it reads "captured", whatever that means ... Now, let's try attaching it... It raises an error with message shown in Digilent_USB_JTAG_attachment_error.jpg "USB device is busy with a previous request" :/ This is sad ... Of course, no other device appears in /dev/tty* Greping dmesg for FTDI pattern returns Nothing. Only UART USB devices appears in dmesg log... I've tried the same test with USB 3 (xHCI) configuration selected. Do any of you have an idea on how I could attach the USB Digilent JTAG device to my Centos 6 VirtualBox machine ? Any help will be highly appreciated. Thanx a lot. Cheers
  10. sdm

    FMC-CE Breaks JTAG Chain

    I've got the FMC-CE board plugged into a ZC706, and when I try to load open the Hardware Manager in Vivado, it finds my HW target, but there are no devices found. After a little digging I found that there is an FMC design rule that if you don't use the JTAG chain you need to tie the FMC TDI pin to the TDO pin. Looking at the schematic, this isn't done on the FMC-CE board. Both of these FMC pins (D30, D31) are disconnected. What's the best way to work around this to enable JTAG debug when this board is installed?
  11. amess

    Parallel FPGA JTAG programming

    The attached image is probably the easiest way to ask this question .. We want to program 6 devices all at the same time using 6 copies of a USB-JTAG device (as opposed to having once large JTAG chain). It looks like Impact / Vivado does not natively support this (it sees multiple dongles but only deal with them one at a time). Can we script something to load a BIT file on all 6 simultaneously? We currently have the XUP USB-JTAG Programming Cable but would switch to another one if this one can't do it. Thanks!
  12. Theo

    Damaged HS2 cable?

    I wonder if I have encountered the same issue as Mojy with my Digilent HS2 JTAG cable. I raise the question again because it looks like the question was answered, but by a private communication. I'm running Red Had Linux 7.4. I've installed the Adept Runtime and Utilities packages. Previously, running djtgcfg enum had listed the HS2 device. Now, it does not. However, the lsusb utility recognizes the device as Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC I see that this is the bridge chip inside the HS2. I think Mojy's original assessment of lost EEPROM may be correct. Can you help? Thanks, Theo
  13. We have recently purchased a JTAG-SMT2 board in substitution of a JTAG-HS2 cable, in order to program a Microzed board with Xilinx Vivado. The same Windows machine that was working with JTAG-HS2 now recognizes the new device JTAG-SMT2 as "USB Serial Converter". We have tried some solutions in other forums, as using FTDIconfig, with no success. What is remarkable is that, when plugging the device, Windows 1st finds a "Digilent USB device", but then automatically installs a driver and it is converted into "USB Serial Converter".
  14. Patrick Fitzpatrick

    HS2 Programming Cable. Multiple Instances

    I have a system where I'm using 2 HS2 cables. One is used for SPI control and the other for Jtag. For my SPI interface, I have written a DLL using the ADEPT2 SDK, that allows me to specify the serial number of teh device to connect for SPI. Unfortunately both devices enumerate as device name "jtagHs2" and If I start my Xilinx Viivado Hardware manager before my SPI interface, the Vivado is taking over the device I want to use for SPI. If I start my spi interface first then vivado correctly picks up the HS2 I want to use for JTAG. Is there a way to prevent this, for example can I change the name "jtagHS2" in my SPI interface eeprom? Thanks, Patrick
  15. Hi, We are going to purchase JTAG-USB Cable to debug our own developed chip. 2 questions here: 1. I assume this JTAG-USB Cable is able to auto-sense my VDD voltage level as long as it is within the range 1.8V ~ 5.0V. Is this correct? 2. We need this JTAG-USB Cable to do some configuration in our chip. Do I use "Digilent Adept Suite" or "Digilent AVR Device Programmer" to generate my JTAG signals/waveforms ? And one request: 1. I need a datasheet of JTAG-USB Cable datasheet if possible. Please advice, thank you. Tifei
  16. JTAG-USB-FTDI

    JTAG-USB Question

    I am interfacing between a USB IC (a FT2232H FTDI chip) and a EEPROM IC (a 93AA56BT). To make the FTDI chip recognizable by Xilinx tools I need licensed Digilent Serial Numbers. How can I get a licensed serial number file to enable a USB-JTAG FTDI interface? Are these licenses keyed specifically to your chips? How can I enable a JTAG-USB FTDI interface?
  17. I'm using the Nexys Video board and I'd like to use the FIFO capability of the FTDI chip (IC13 connected to J12) to get data from the FPGA quickly and easily while keeping the JTAG lines high-impedance. I would like to use the FT2232H FIFO port while using our own JTAG (J17). The JTAG lines on that chip are high impedance until the USB cable is plugged in and I'd like to keep them high impedance while using the USB port. If you don't know, can you send me the schematic page for IC13/J12?
  18. Hello, I bought Arty-A7 development board and I will use it for Risc5. How can I connect a host pc to this board for using openocd? This board has 'FT2232HQ' and does it mean that I can use USB port for JTAG and UART at the same time? (Or should I buy any other cables for using openocd?) Thanks,
  19. diannaodanshi

    JTAG SMT1 SMT2 compatibility

    Hi, Recently, the JTAG SMT1 on our Xilinx VC709 FPGA board is physically broken (and we are sure that the only broken part on this board is JTAG). However, it seems that JTAG SMT1 has retired and the only available one on your website is JTAG SMT2. So I want to know if we can replace the broken SMT1 with a new SMT2. In another word, is SMT2 compatible to our board? Thanks.
  20. smarano

    eFuse Programming

    Hi I'm tring to program my cmod a7 35T Digilent board with an encrypted bitstream. I read that to do this i need to program the eFuse register with a key.nky file, but when i try to do this i found a problem. This board don't have a jtag connector but it can be programmed via usb. When i try to program efuse a found a problem "cannot program efuse register with this cable". Anyone can tell me if there is another way to program efuse or if this board can't support encryption bitstream? regards Stefano
  21. RYO

    [Arty] signal order of J8 port

    Hello, everyone. We are planning to access JTAG by attaching a pin header to J8 of Arty board in order to confirm efuse access. (I dont use USB-JTAG.) Which signal corresponds to each of the six through holes of J8? I check the reference manual and circuit diagram, but there is no clear description. From the relationship with the D1 diode on the circuit diagram, I guess the following order. Is it correct? 1. TMS_JTAG (suquare, 1 pin mark?) 2. TDI_JTAG (circle) 3. TDO_JTAG (circle) 4.TCK_JTAG (circle) 5. GND (circle) 6. VCC 3 V 3 (circle) best regards, ryo
  22. gm_

    JTAG HS2 completely silent

    Hi all, I have just tried my JTAG HS2 on 4 PC with windows and linux, but the device is not recognized by any of them. I also tried to change the usb cable to no avail. Any idea to what else I could do before sending it back? Thanks!
  23. Dear all, I would like to buy JTAG HS2, but I have the followings doubts: 1. is it recognised by Fedora? 2. does it support debugging? 3. does it work with urJTAG? 4. is it compatible with openOCD? Thanks! gm
  24. skaat27

    arty Z& petalinux BSP Error

    Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here https://github.com/Digilent/petalinux-bsps/wiki/Quick-Start-Guide-for-Arty-Z7. But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  25. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.