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Found 13 results

  1. Hi, First thing first. I am a starter in the fpga custom design. I have done few simple projects codes in Digilent virtex 5 board but now circumstances requires me to get more IO pins. I will, in this section mention first what I am planning (English is not my first language sorry for any errors). 1) I am using XC6SLX9 2) Route the VCCAUX, VCCINT, GND, 100MHZ single ended clk. 3) Route out the JTAG pins (namely TMS, TDO, TDI, TCK) 4) I am using ISE 14.7 5) 1) I just want to generate gate signals. In this section I shall lay out what help I want. 1) Is what I have done enough to program the spartan 6 device via JTAG? (I know it will be volatile) 2) Can I program it using the JTAG HS3 cable? (someone said that I need the platform cable to program and HS3 only works with series 7 ics, but platform cable would cost too much for me at this moment) 3) For a 14pins (7 pins in 2 row) JTAG connector, what other routing I need to consider from the FPGA (except the 4 JTAG pins mentioned in the previous section) . Any other help or information that I need is extremely acknowledged. FYI: I am also attaching an approximate final outcome that I want.
  2. Hello, I have used the digilent JTAG-HS3 programmer simultaneously with other device with FT232H chip and I have probably erased by accident the FT232 chip on Digilent module or there is a problem with drivers - the device is still recognized as Digilent USB serial converter by the system so I think is not damaged, but the cable is not visible in xilinx software. Could you please help me?
  3. Hi I have two of the HS3 both of them show as USB serial converter. What should I do?
  4. Hi, I have the same problem as here but with a JTAG-HS3 : Very hot at the bottom right near the "A". It is recognized in Vivado and Adept (SN:210299A568D8) but not my FPGA and Flash It's a custom card that's been working for several months. I tested with 2 cards and it's the same. Vivado error : Is my HS3 dead? Thanks, Stéphane
  5. Hi, We have bought two JTAG-HS3 debuggers. One of them works perfectly, but the other one keeps returning: "1 whole scan chain (device configuration stabilizing)" or "1 whole scan chain (device configuration unstable)" when using the "targets" command. Any idea what could be the problem? Best regards Lars
  6. We are using several copies of the JTAG-HS3 programming cable in our lab to load programs to a Xilinx Ultrascale+ device using Vivado via JTAG. Sometimes we can load at 15Mhz clock speed and succeed, sometimes we must cut back to 10MHz to be successful, and sometimes even 7.5MHz when dealing with the same board at different times. Since it is a big program into a big part, higher speed matters. We have tried the standard cable wiggling and swapping cables, but still have not found consistency. Is there some issue that others have seen, updates that need to be applied, or anything else that may explain the variability? Any feedback appreciated. Thanks. Mike Placke
  7. Hello All! I am currently working on designing a carrier card for a board that uses a Zynq Ultrascale+ mpSoC (XCZU2CG) and we want to use the JTAG-HS3 to program the SoC via the carrier card. The HS3 datasheet states "To function correctly, the HS3’s Vref pin must be tied to the same voltage supply (VCCO_0) that drives the JTAG port on the FPGA." This 1V8 supply however is not available on our carrier board (it doesnt leave the SoC board). We do have access to a 3V3 supply from the SoC board. Can the JTAG-HS3 function if we connect the Vref supply pin to a 1V8 LDO Regulator powered from the 3V3 of the SoC board? Any help on this is much appreciated.
  8. Hi Folks, I am working with Xilinx Zynq7020 SOC Chip. Also, I am using Digilent JTAG-HS3 Jtag. I made design in vivado 2015.2 and HLS IP block also made in Vivado HLS 2015.2, design is checked in SDK 2015.2 is working fine. Presently, i upgraded to 2016.4 vivado package and upgraded the 2015.2 design to 2016.4. validates the design and generate bit stream in 2016.4. Running the design in SDK 2016.4 with source (C) files. Initially i restored the image into DDR3 physical address location, in SDK Log showing restore successfully,After as soon as this error showing (in Attached image),without running the code . I checked with different PC's also, same error. what is this problem and i am unable to understand it. whether the problem with Tool or with my design . Please find the attachment. Please suggest me the solution regarding this Problem. Thanks and Best Regards Vinod Sajjan
  9. Hi everyone ! I'd like to use the JTAG-HS3 cable to work on a project which consists in testing several interconnections between devices on a board. I'm using DJTG and DMGR APIs and i'm connected via ssh to the computer which has the cable plugged on. My question is: How do i connect to the board with the DMGR API? I know that i have to use DmgrOpen() function but it requires a "device name", which i don't have. Thanks in advance ! Have a nice day !
  10. Hi, We would like to use several Digilent JTAG-HS3 cables (up to 8) on a PC with Linux via one or several USB hubs since the number of USB ports on all computers is limited but we currently don’t manage to make working a single JTAG-HS3 with a PC with Linux via a USB hub. We tested on two different usb hubs (1 dedicated device, 1 integrated to a screen) and computers (1 desktop, 1 laptop) but the only configurations which work are: no usb hub and either a usb port of the laptop or a usb port on the rear panel of the desktop. Can someone say us if similar issues are already known with this cable and/or test such a configuration by its own and come back on this thread? The Impact version to use is the 14.7 one. Best regards, Vincent
  11. abe

    JTAG-HS3 vs JTAG-HS2

    We wish to purchase a few more programming pods and would like to know if we should purchase the JTAG-HS3 or the JTAG-HS2. In the past we bought the JTAG-HS2. We are using an ARTIX-7 and a KINTEX-7. (On another project we use the ZYNQ-7000). When should I buy the JTAG-HS3 and when would I buy JTAG-HS2? What is the advantage of one over the other and what does one do that the other does not do?
  12. Count0

    Moving to Linux

    Hi all, i'm moving my development environment to Ubuntu. Last things I'm struggling with are Xilinx WebISE and the JTAG-HS3 programmer. All worked fine under W7pro. But WebISE performs traumatically on Ubuntu. WebISE was designed to run on RedHat and SUSE but it runs there far from flawless. So I put up a W7 in VirtualBox on Ubuntu and got WebISE running fine again. But when forwarding the JTAG-HS3 to the VM, the VM got killed immediately. I can live with this situation if I knew how to operate JTAG-HS3 on Linux, to upload a bitstream to my FPGA. So my questions boil down to: Where can I find a user manual about how to use the Adept software for Linux. I haven't found it on the Digilent website?Does anyone know how to stop VirtualBox VM's crashing when connected to a JTAG-HS3 programmer? Thanks in advance
  13. Hello, I currently use a JTAG-HS2 cable with my Zynq development board. What would be the advantage or disadvantage of switching to a JTAG-HS3 cable with (exclusive) regard to using it with Zynq devices (Through Vivado 2014.4 and SDK)? I found this comparison table : I think the big difference towards Zynq is the PS_SRST support, however it's not clear to me what exactly this is? I can use the Zynq now with my HS-2 cable, put breakpoints, ... so I wonder what this extra feature might bring to the table. I guess the 'no support for 2-wire JTAG' and SPI' is not an issue with Zynq devices (?) best regards