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Found 11 results

  1. Hi, I want to setup a high-school project for my son, I have no previous experience with FPGAs. A friend recommended coolrunner II starter as a platform. Dev env is not clear to me, Digilent point to Xilinx Webpack, but it seems this one merged in a 6.8GB ISE Design suite package. Questions: 1. Should i use the Xilinx 14.7 ISE as "webpack"? 2. It looks like this ISE is no longer supported, specifically it does not support Windows 10. Any way around that? 3. Does it mean that CoolRunner II is deprecated and I should use other starter kit board? 4. If so, can anyone recommend a starter kit for FPGA that is not deprecated?
  2. This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. Note, that ADC used external reference voltage of 2.5V to match the reference voltage of DAC. The current level of the voltage feedback signal is displayed on the on-board 8-digit seven segment display. a2d.vhd brgen.vhd clock.vhd dig2an.vhd disp.vhd fbin2bcd.vhd func_gen.vhd ibin2bcd.vhd rx.vhd ssd.vhd tx.vhd Nexys4DDR_Master.ucf func_gen.m
  3. Victor McKeighan

    Victor

    I'm using Xilinx ISE suite to design, test and program the Cmod S6 board. At this point I am able to configure the Spartan6 FPGA with a bit file over the USB connection (although I have not verified functionality), but I'm having a problem programming the serial PROM. Here is the report I get from the iMPACT tool: INFO:iMPACT - Current time: 5 Jul 2018 14:00:55 // *** BATCH CMD : Program -p 1 -dataWidth 1 -spionly -e -v -loadfpga PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 25000000. Validating chain... Boundary-scan chain validated successfully. '1': IDCODE is 'ffffff' (in hex). '1': ID Check failed. INFO:iMPACT:2488 - The operation did not complete successfully. INFO:iMPACT - SPI Device not found. INFO:iMPACT:2488 - The operation did not complete successfully. INFO:iMPACT - '1': Flash was not programmed successfully. PROGRESS_END - End Operation. Elapsed time = 4 sec. It seems to fail the ID Check, whatever that is. When I selected the PROM device, I chose S25FL128S from the available list. I think that is the correct one. Also, if I try to erase the PROM or do anything else with it, I get a similar error. I tried following instructions posted on this forum, but nothing seems to work.
  4. Hello, im new on this forum. Im trying to learn how to use a extern DDR2 RAM that my Virtex 5 have. I honestly dont know the step by step. I do this to learn how to use the FPGA in order to gaining experience for a future proyect. The most difficult module that i used was the Display and works fine. Im using ISE 14.7 With the DDR2 RAM the only thing i did was creating the file that Core Generator Tool provides after the first configuration. I had a problem there: i couldnt assign all the ports but i was able to create the file anyway. Now i'm not shure what to do next. I'd apreciate any help that someone can provide or some tip to follow. Sorry but im a little lost in this subject. I have a Virtex 5, XC5VLX50T. Thank you!
  5. A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: 192.168.1.10 Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use any input or output FIFO's as elesticity buffers,both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes, which allows better resource utilisation at the price of, probably, more complex design architecture. Design is implemented in VHDL using ISE by Xilinx. Below there are the source files for the echo-server projects along with .m file to transmit/receive data using MatLAB. Figure "wireshark_capture" illustrates the data traffic between FPGA board and data server (MatLAB); Figure "TxRx_Error" compares transmitted data against the data received from the board. UDP echo-server manual.7z UDP echo-server.7z
  6. Hey there I'm thinking about purchasing a Zybo or Zedboard to Implement a SDR application. I'm in electronics engineering student with microcontroller history but brand new to FPGAs. I have a few questions about the vivado license, ISE vs Vivado for DSP applications. What exactly is it that the licence that Digilent sells offer that the webPack dosent? I have read here on the forums about some discrepancy between the Vado licenses and forgot it updates in this regard. Is the CihipScope offered in the wet pack now? I may later decide to purchase the SDR software package offered by AVNET, or at least individually accumulate those licenses as my budget allows. So how dose the webpack version limit my ability to integrate with the software elements(currently unable to find the said software package) used for SDR & DSP development? What are the limitations of the Pmod interface if I were to go with the Zybo and later try to coonect to a FMC interposer/Analog Devices ACD boards? Im reading the zybo book but any links to more learning resources would be greatly appreciated. I'm ready to pull the trigger on a purchase today as soon as I get these questions answered. Looked high and low for a phone number
  7. sketchn98

    Add board to ISE

    In ISE's new project wizard there is a section for "Evaluation Development Board". I'm using a board that is not on the list and would like to know how to add one to it.
  8. Hi I am new here. My background is I used ISE 10 but mainly used the schematic capture and the FSM software for my designs. I used a little VHDL and Verilog from the library to form some blocks for my schematic projects. For the most part my designs have all centered on Schematics. I have some unique design blocks for full projects I did with the finite State machine software. I have in stock has a Nexys 2 board with a Spartan 3500E on it and I was planning to use for a demo model when I found out this board is being discontinued. I like the 7A100 you have on the Nexys 4. This will multiply my capabilities compared the old board I had. I also downloaded the Vivado series design tool and found it very powerful in some aspects to ISE. I lost my connection to someone that can write code and Tcl script. I need to get this demonstration model done ASAP so I have the following questions. I see you cannot migrate schematic files to Vivado. I don’t want to migrate complete projects just the blocks of circuits in them especially the ones I generated from the FSM software which is converted to VHDL and Verilog. Can I make custom IP’s from them and use them in Vivado? Are there files I can take from my old ISE project circuit blocks and can use in my IP catalog and Vivado? In the IP catalog I don’t see some circuits I need in my design.I don’t have time for a learning curve. Is the Vivado software a software that requires more knowledge and experience concerning writing code than I have (which is limited)? If I can handle the learning curve using the Vivado design tools in a descent amount of time, I want to use the Nexys 4 with 7A100 in it. If I can’t then I will have to use the Nexys 2 board that has. the Spartan 3500EWhat kind of prerequisites in learning do I need to perform a successful project in Vivado?Thanks Rex
  9. meiyas

    Basys 3 With Ise Webpack

    Hi Can I use ISE webpack with the basys 3? I already have basys2 that I use with ISE webpack and was planning to buy basys3 now that I need more, but I wanted to know if I can continue to use the same software. I think you can't use vivaldo with basys2 but i can't find info if basys 3 can be used with the ISE webpack! Thanks!
  10. Hi, I've been working for a while now to create a program which generates a specific signal. I think I may have succeeded but I don't know how to verify that. I was hoping that there would be a way to use the Diligent Adept software or Xilinx ISE to see what my board is outputting. Hardware/software; Im using A nexys 4 board, ISE 14.7, and adept 2. The code I have was generated by Matlab's hdl coder and the out puts are two 10-bit signals. Thanks.
  11. A customer asks me the following question. I would like to share in the forum. Question: We want to know where we can find out documentation or media or resources? Answer: You can download the Xilinx Webpack and Impact at the xilinx.com. Regarding the documentation, you can go to the product webpage http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1000&Prod=CR2-STARTER. It has schematics, reference manual and a demo file.