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Found 6 results

  1. Dear all Please help in accessing ethernet port of Atlys FPGA board. Is it possible to access ethernet port using available IP in ISE or I have to write protocol for it. please reply if anybody has done that. -- Gopal krishna
  2. Hi, i also Facing the same issue.. I'm setting up the Spartan 3E system using VM( VirtualBox -Win7 IE8) with installed with ISE 14.7 on my WIN 10 PC. the USB connection showed in Device Manager is Xilinx USE Cable, but when I run the IMPACT to program the FPGA it show the error below: Error: GUI --- Auto connect to cable... INFO:iMPACT - Digilent Plugin: Plugin Version: 2.5.2 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz re
  3. HI , i faced an issue to program the FPGA to my Spartan 3E board. WARNING:iMPACT:923 - Can not find cable, check cable setup ! My setup is using VM(Win7) with ISE 14.7 installed on my Win 10 PC. im using JTAG cable to program the FPGA, i try to download the Digilent Plugin Tool from here https://store.digilentinc.com/digilent-plugin-for-xilinx-tools-download-only/ but no response... can any one share me the ZIP files? or the files is corrupted ?
  4. Greetings, Just bought the Nexys A7-100T was using Nexys 2 up until now. Currently using ISE 14.7 looking for the User Constraints file for this board in the resource page nowhere to be found. There is in the examples a .xcf file which does not help me at all. Tried to type in a simple .ucf file no luck there example below. Tried to use the .xcf file that does not work. Renamed the .xcf file to .ucf file that does not work. NexysA7.ucf Frustrated with new board cannot even get it to make a simple Adder. I receive the following error when generating the bit file. I h
  5. Hello everybody, I'm developing a project using a Zybo Board. I'm on an early stage, right now I'm just trying to print out on a screen 640x480 an image from a rom memory (depth 1024, width 12) created using the Core Generator (I'm writing the project in Xilinx ISE 14.7). However, the result on the screen is not what I expected... First of all, I've created my rom memory containing the image: it has been converted in bitmap format and then translated to a vector of 32*32 cells (the image is 32x32 pixels), each one containing a string of 12 bits representing the color of a pixel, usi
  6. Hi Everyone, I am developing a design based on ISE 14.7, Artix-7 CSG324 NEXYS4 eval board. For testing purpose, I wrote a simple clock divider code as following, but the compiler keeps warning me: Line 31(red line): Result of 32-bit expression is truncated to fit in 1-bit target. The RTL schematic looks the same as I expected, If ignore the warning and program the eval board, clock frequency wouldn't change when SW0 - SW3 input changed. I wonder if it is because of compatible issue for the compiler(most people use vivado for artix-7)? But on the Xilinx website it says the ISE wi