Search the Community
Showing results for tags 'ipcore'.
Found 3 results
Hello everyone, I’m a newbie on working on zedboard, and I want to use my Zedboard to communicate with Pmod MIC3 this time. I did a few researches about how to use the Pmod MIC3, and I think I found something useful in another post, link: https://forum.digilentinc.com/topic/19342-driver-code-for-pmod-acl2-and-pmod-mic3/ I’m really appreciate and thanks for their help, but unfortunately I still have no idea of how to make my Pmod MIC3 to run with my Zedboard. I know Pmod MIC3 is using SPI communication protocol and I read what SPI is, link: https://reference.digilentinc.com/learn/fundamentals/communication-protocols/spi/start But I’m not sure is that Quad SPI is the same as SPI in Zedboard. About the Pmod MIC3, I know that it used a MEMS Mic and an ADC, but I also don’t know how to implement it, like do I need a code or IP cores to handle these 2 components? Here is a simply conclusion of my questions: 1. How to use SPI in Zedboard? (Any pin configuration is required?) 2. Do I need a code or something else to handle the ADC and MEMS Mic in Pmod MIC3? 3. Is it possible to make this project work in .vhdl? Or I need something else? 4. How to getting start with? 5. Importance of IP core I know IP cores is an important thing, but I don’t get a clear idea about it and how it works with Vivado. Any help and reference suggestions is appreciated! Thanks 😊 !!
Hello, I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core. Can you helo me about these issues as soon as possible? Thank you. Best Regards.
Hi, I am trying to compute FFT of a synthesized square wave of frequency 100Hz. The 100Hz signal has to be sampled at 1kHz. So, I kept the clock frequency of FIFO, FFT_IPcore and other blocks at 1ms. I have attached the screenshot of the design file and simulation results. From the simulation output, it can be observed that the buffer stores for 512 samples and the un-buffer after 512*1ms. But, there is no output from the FFT block. I would like to know whether my approach is correct or I am committing any mistake in the way the blocks have to be integrated. Help much appreciated. Regards, Subash