Search the Community

Showing results for tags 'ip'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 21 results

  1. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
  2. Hello all, I've been working on an audio looping project which requires DDR3 memory for audio sample storage. After setting up the MIG-7 according to the Nexys Video Reference Sec 3.1 and reading through the 7 Series FPGAs Memory Interface Solutions User Guide, I'm at a loss for why the memory component won't initialize. I'm including a link to my repo here, but I'll try to explain my implementation in detail below: Clocking: Using the settings recommended here by @elodg, I set up an IBUFG in my top level file, feeding a clk_wiz instantiation in the file containing my MIG. This also involved setting up a clock backbone route in my constraint file. Instantiation: I've been instantiating my MIG with inputs set to 0 (except clocks) and outputs left open, just trying to get that init_calib_complete signal to go high. clk1 : clk_wiz_0 port map ( -- Clock out ports clk_out1 => clk_ref, -- Status and control signals resetn => reset_n, -- Clock in ports clk_in1 => sys_clk_ibufg); u_mig_7 : mig_7 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, init_calib_complete => init_calib_complete, ddr3_odt => ddr3_odt, -- Application interface ports app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => (others => '0'), app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => open, app_rd_data_valid => open, app_rdy => open, app_wdf_rdy => open, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => open, app_ref_ack => open, app_zq_ack => open, ui_clk => open, ui_clk_sync_rst => open, -- System Clock Ports sys_clk_i => sys_clk_ibufg, -- Reference Clock Ports clk_ref_i => clk_ref, sys_rst => reset_n ); Constraints: I have one user constraint file bringing in the 100MHz clock from the board as well as buttons, switches, leds, and the audio codec signals for debugging and other functionality. It's attached to this post. MIG setup wizard settings: If anyone has experience with using this MIG or any clocking expertise, please let me know. I've been banging my head against this just hoping for a calibration, and I would really appreciate your help. Thank you!
  3. hey everyone, I am trying to generate different waveforms of analog signals using ZEDBOARD + PMODDA2. My previous question was about Pmod+zedboard. Then, I was able to simulate the example verilog code (pmod_da2_demo) and -after changing the constraint file (.xdc)- i generated the bitstream and programmed the FPGA on my ZEDBOARD. This example piece of code generates an 12-bit digital input to the DAC and the output is expected to be a triangular waveform whose output amplitude is in between around 1.5 and 2.5 Volts. When I checked the output on the o-scope i have obtained the following wave. However, I want use both PS and PL parts of the Zedboard. That is why i need a block design which will have ZYNQ7 PS + AXI interconnect + Processor System Reset etc plus my PMODDA2's reference component i.e. DA2RefComp. DA2RefComp's inputs are CLK,RST,DATA1,DATA2 and START. If I package DA2RefComp as an IP its GUI looks like as the following: The other option is to make an RTL module using the given DA2RefComp.vhd as shown below. I tried to make the RTL module to work with Zynq7 PS. Then reading from the forum's suggestions, I tried to make the following circuit. Using AXI GPIOs and AXI Int etc are connected automatically. The triangle_0 IP module just generates triangular wave. MY question is this connection below seems correct? I couldnt make it work, yet. Secondly, the CLK input of DA2RefComp requires 50 MHz input so should I divide the clock of the PS? What should I do with the RST input of DA2RefComp? Is it just good when connected to the other resets automatically?
  4. Hey All, I am trying to make a simple IP block design in Vivado 2018.3 to test the ESP32 PMOD out using AT commands for data transmission. I will attach a picture of my current block diagram to this post. I am getting a critical error (reference below) that says the IP has a packaged board value of "" which is for the Zybo z7 board. My questions are: Q1)Will this design work regardless of this error, as the Zybo and Zed boards are similar and both run off the zynq-7 architecture? Q2)If the answer to Q1 is "no", is there a method of adapting this IP for the Zedboard? (I should be using the latest IP library from Digilent) [IP_Flow 19-4965] IP PmodESP32_axi_gpio_0_0 was packaged with board value ''. Current project's board value is ''. Please update the project settings to match the packaged IP.
  5. We are suppose to add a library from here: and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  6. I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: I have a Video Test Pattern Generator connected to an Axi4-stream to Video Out IP driven by a Video Timing Controller IP. Here is a 100 ms simulation for the circuit: Vsync does not get generated, so clearly there is something wrong with this circuit. All examples I have found online include a MicroBlaze or Zynq processor with their design connected to the VTPG, could this be a reason my circuit is not working? Is it possible to do what I am trying to without a processor? What exactly is the role of a processor in these circuits? My development board is a Nexys 4 DDR. I've gotten VGA to display in the past using IPs I created myself, but they weren't AXI compliant. I have attached the tcl file to build my block design Any guidance would be appreciated! design_1.tcl
  7. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  8. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: CSI-2 Camera: DLP 2000 RGB - projector: HDMI projector: Display : Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  9. This question came up on a previous thread and I wanted to ask it separately According to the Digilent rgb2dvi IP specs, "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" My video is 720x576, with a 27 Mhz pixel clock, which is not supported as is In the previous thread, @hamster said that it is possible to customize the IP by changing the divide-by values in the clkgen. Can someone help me with this? Has anyone ever had a similar problem? Also, how will I deal with the lower pixel resolution?
  10. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo
  11. sandy

    zybo DVI to RGB

    I have been trying to use digilent DVI to RGB IP for zybo board, the pixel clock from the ip gives an output of 100MHz , is there any way to reduce the pixel clock frequency , if so can someone please tell me how.
  12. Hi, I'm using the dvi2rgb/rgb2dvi cores (latest repository version) to make a simple passthrough in the FPGA and have huge issues with the EDID memory. Has it been confirmed at some point that the default 720p edid settings work properly with a GoPro Hero5 camera? I tried loading the default EDID, a properly cooperating monitor's EDID, prepared numerous EDIDs myself - every single one seems to fail so the camera is setting itself to the lowest supported resolution. Had a go with a Panasonic DMC-G3 camera too but it behaves the same way. Both sources work properly when connected directly to the monitor. The EDID values are being read properly, this has been verified on an oscilloscope (the camera seems to be reading the 128 edid bytes twice though).
  13. Hi, I'm trying to install a module driver in my petalinux rootfs for using on zedboard. I configured an IP core for PL, which has two AXI memory mapped ports (pic1). Now, for using my driver which is responsible for communications with my IP core, i need to know the conversions from phisical addresses to virtual addresses made by kernel. At installation i see just one conversion (S00 is Lite and S01 is Full) : [email protected]_2:/lib/modules/4.9.0-xilinx-v2017.2/extra# insmod driver-mihaiv1.ko [ 1324.279333] <1>Hello module world. [ 1324.282663] <1>Module parameters were (0xdeadbeef) and "default" [ 1324.289030] driver-mihaiv1 43c00000.accHW: Device Tree Probing [ 1324.294839] driver-mihaiv1 43c00000.accHW: no IRQ found [ 1324.299993] driver-mihaiv1 43c00000.accHW: driver-mihaiv1 at 0x43c00000 mapped to 0xe09c0000 In pics you can see the phisical adresses for my IP core. As i see, just the first phisical adress has a virtual conversion <0x43c00000 to 0xe09c0000>. Has anyone met this problem?
  14. Hello,I kindly ask you to send me information about FPGA boards with the ability to measure the power consumed by the IP.kindly note that the aim of this question is to have a board that supports the power consumption measurements on the FPGA itself .So please inform me if is it available such kinds of fpga boards with this features to evaluate the power consumption.Merci!Yehya NASSER,
  15. bino

    Connect my IP module

    HI ! First : I'm a new in FPGA development For my experiments, I designed an IP module (in Verilog), which takes 3 inputs (clk, rst, walk[7:0]) and drives in funny way leds. Decided, that it's too much for this to use AXI memory mapped interface and used for control signal only 8-bit vector. My question is : can I use AXI GPIO with 8 bits output and connect only it's output vector to my IP's "walk" ? As I tried, the default value from GPIO works, but couldn't drive this value from the SDK at the address of the AXI GPIO ? Or may be some more clean way ? Sorry, forgot : I test the design on Zybo.... Thank you in advance ! design_1.pdf
  16. I want to use the flash memory of 32Mbits of the basys 3, to write data in hexadecimal, I am using microblaze and the IP block axi quad spi, I have configured the hardware in vivado, i have included the soft-core microblaze and I have added the IP block Axi_quad_spi and I have connected the ext_spi_clk, s_axi_aclk (synchronously), with the 100 MHz clock, automatically vivado connected the outputs to the pins of the flash memory of the basys 3 card, so my question is: to program the memory in the SDK of xilinx, is there an example already done with this memory ?, or how can i program it?
  17. Greetings everybody, I recently purchased a Zybo (Zynq 7000 series application board), currently I am experimenting around with it a bit. This is the first time I am working with FPGAs, up to now I have only been working with other microcontrollers and cortex processors. While looking for reading material, I stumbled across this example, which shows how to create and use custom IP cores using Vivado. Since it is an official example from digilent and other examples worked without problems I though this one would be easy to follow, too. Problem is, it doesn't work. I am following each and every step exactly as shown in the pictures and described in the text. After successfully generating the bitstream (no warnings/errors) and exporting it I run the SDK. The C code there compiles, too, I program the FPGA and launch the compiled ELF using GDB on the Zynq. Here I first have to turn off the "Run ps7_init" and "Run ps7_post_config" checkboxes in the run configuration, otherwise the elf won't run on the Zynq. Now the ELF runs on the Zynq (or at least I hope so...), but nothing happens. Nothing at all. The LEDs are supposed to start pulsing, but they don't. Does anybody have similar experience with the given example? Or can anyone tell me what's wrong or how to find out? I'm greatful for any help you might have to offer. I currently am using Vivado 2015.4 (64 bit). Best regards, Daniel
  18. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?
  19. Is there a users guide for the open source Digilent IP Stack. The examples are encouraging but don't provide as much information as do the Microchip MALs.
  20. Hi How would one expand access to all the output bits of a IP like a binary counter to be able to access the binary out with other IPs. For kicks say you want to OR counter out bits 0 and 2. If you have any suggestions or questions please let me know....Thanks Gus50310
  21. I realised a Vivado ip axi controller for basys3 4 digits display. You can find ip and test project here It's easy to expand for nexys4 8 digit display. Actually the controller manage the number of digit to use in hex or bcd mode with the limitation of overflow. Dp are not managed. It will be helpful if Digilent can develop some ip templates for Pmod modules .... just a suggestion