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Found 5 results

  1. Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect Pmod DA3 clock to XADC clock creating a unique clock for the entire design. This design was validated. Creating a HDL Wrapper, it has a correct synthesis, implemetation and bitstream. Programing the board i dont get any analog value for output Pmod DA3, it only works output LED[15:0]. Modules works correctly independently. Should i make a different connection for clocks? I dont know if there is a clock problem or other type problem. i attach the project Can anyone help me? Thanks! XADC + DA3.rar
  2. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its ports are compatible and I can connect myblock between axi_gpio_1 and rgb_led? A more general question: what would you recommend as a next level of tutorial to study so that I wouldn't have to ask the questions above? I've looked on the Xilinx site, but the amount of documentation is overwhelming. I don't know where to start! Here is myblock.v and part of my block diagram:
  3. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h> #include "ap_cint.h" int PRBS_prj(int bit) { #pragma HLS INTERFACE s_axilite port=return bundle=a int start_state = 0xCD; int lfsr = start_state; unsigned period = 0; do { /* taps: 3, 2 and 1 ; feedback polynomial: x^3 + x^2 + 1 */ bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1; printf("%d", bit); lfsr = (lfsr >> 1) | (bit << 7); ++period; } while (lfsr != start_state); return bit; } or int main(void) { static int lfsr = 0x3425u; unsigned int mask = 0xF0; int bit; /* Must be 16bit to allow bit<<15 later in the code */ //taps: 16 14 13 11; feedback polynomial: x^16 + x^14 + x^13 + x^11 + 1 bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5) ) & 1; lfsr = (lfsr >> 1) | (bit << 15); for (mask = 0xF0; mask; mask >>= 1) putchar('0' + !!(lfsr & mask)); return lfsr; }
  4. Hello there, I have developed a fixed point design, then an IP core for matrix multiplication using vivado HLS.I need to deal with fixed point data types in Vivado SDK to send data to a fixed point IP core.Does anyone has any idea of how can i go about.?Thank you
  5. HI there, I have a simple HLS design which I exported as an IP Core to implement on my target. But I get the following error when I go ahead interconnecting the IP cores. Does anyone have any idea as to how I can work around this obstacle? I even tried changing the frequency of the ports, but the fields are inactive. [BD 41-237] Bus Interface property FREQ_HZ does not match between /matrixmul_0/INPUT_STREAM(100000000) and /axi_dma_0/M_AXIS_MM2S(200000000) [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_dma_0/S_AXIS_S2MM(200000000) and /matrixmul_0/OUTPUT_STREAM(100000000)