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Found 7 results

  1. In all example project I could found, rgb_led is driven from a GPIO block. That works well but I need to drive it from a row of XOR gates and so far I could not convince Vivado to connect the output of the XOR to rgb_led. If you look at the attached picture, the goal is to connect "Res" or "BUFG_O" to rgb_led (which seems to have a 12 bit input since the GPIO which was driving it in the sample project is 12 bit wide). Does anyone know how to do ?
  2. Hello, I've been working on a project that I need to use the ip integrator and add an RTL block that I made. I'm using a Basys 3 board, Vivado 2018.3 and MicroBlaze ip. I was trying to add the RTL to the source and to the diagram and I used the getting started with ip integrator tutorial. The tutorial itself worked fine and when I added the RTL It passed the validation, synthesis, implementation and even generating the bitstream but then I couldn't export hardware for programing the MicroBlaze and it gave an error saying "Cannot write hardware definition file as there are n
  3. Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect
  4. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its
  5. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h>
  6. Hello there, I have developed a fixed point design, then an IP core for matrix multiplication using vivado HLS.I need to deal with fixed point data types in Vivado SDK to send data to a fixed point IP core.Does anyone has any idea of how can i go about.?Thank you
  7. HI there, I have a simple HLS design which I exported as an IP Core to implement on my target. But I get the following error when I go ahead interconnecting the IP cores. Does anyone have any idea as to how I can work around this obstacle? I even tried changing the frequency of the ports, but the fields are inactive. [BD 41-237] Bus Interface property FREQ_HZ does not match between /matrixmul_0/INPUT_STREAM(100000000) and /axi_dma_0/M_AXIS_MM2S(200000000) [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_dma_0/S_AXIS_S2MM(200000000) and /matrixm