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Found 4 results

  1. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.
  2. Hi, I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB. This differential signal will be an input to a buffer on the FPGA. The current xdc file on github uses LVCMOS33 as a default standard as shown below. set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] Would it be fine if I use LVCMOS33 or should I use another IO standard and if so which one should I use. I am using the Arty A7 100t board. Thank you
  3. Hello everyone, I'm migrating my ancient project from the Nexys2 to the Nexys Video, in UCF, the Hirose FX2 signals on the Nexys2 were declared as LVTTL I/O standards, while the FMC signals are declared as LVCMOS in the XDC files provided on the Digilent Resource Center. After doing some researches, I know that LVTTL and LVCMOS differ by their input voltages. In the paragraph of Power Supplies in datasheet of the Nexys Video, il mentions " An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care must be taken to disable the regulator first by bringing "VADJ_EN" low, setting "SET_VADJ(1:0)" and enabling the regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these signals." The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine connector, user push-buttons, switches, XADC Pmod connector, and the FPGA banks connected to these peripherals (banks 15, 16). Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL?
  4. I'm having problems with IOSTANDARD specifications on the PMOD ports of the ZYBO. My design utilizes most of the PMOD ports, namely JB-JE, and on one of the ports I want to output a 2.5V LVCMOS signal (named "Sync"). The other signals are all 3.3V LVCMOS. Trying to implement this on the ZYBO yeilds the following message: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 1 with : SioStd: LVCMOS25 VCCO = 2.5 Termination: 0 TermDir: Out RangeId: 1 Drv: 16 has only 0 sites available on device, but needs 1 sites. Term: Sync Attached is an example of my .XDC file. It's a bit messy since it was created manually first, then edited with the I/O Ports window. I'm wondering if it's possible to do what I'm asking. From my research, it sounds like there aren't enough I/O Banks to support so many outputs, with one output requiring a different VCCO. Is this accurate? iostandard_problem.xdc