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  1. Hello all, I'm trying to use XADC aux channel-6 outputs as input to my unit under test. The CFBLMS module has input parameters for every change in the MEASURED_AUX6 voltage. Can you help me how to do that? Below is the code, and bolded is the part where I wish to take every change in the value of MEASURED_AUX6 as a separate input parameter. `timescale 1ns/1ps module ug480_tb; reg [3:0] VAUXP, VAUXN; reg VP, VN; reg RESET; reg DCLK; wire [15:0] MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX; wire [15:0] MEASURED_VCCBRAM, MEASURED_AUX6, MEASURED_AUX7; wire [15:0] MEASURED_AUX14, MEASURED_AUX15; wire [7:0] ALM; wire OT; wire EOC; wire EOS; wire [4:0] CHANNEL; initial begin DCLK = 0; RESET = 0; end always #(10) DCLK= ~DCLK; // Instantiate the Unit Under Test (UUT) ug480 uut ( .VAUXP (VAUXP), .VAUXN (VAUXN), .RESET (RESET), .ALM (ALM), .DCLK (DCLK), .MEASURED_TEMP (MEASURED_TEMP), .MEASURED_VCCINT (MEASURED_VCCINT), .MEASURED_VCCAUX (MEASURED_VCCAUX), .MEASURED_VCCBRAM (MEASURED_VCCBRAM), .MEASURED_AUX6 (MEASURED_AUX6), .MEASURED_AUX7 (MEASURED_AUX7), .MEASURED_AUX14 (MEASURED_AUX14), .MEASURED_AUX15 (MEASURED_AUX15) ); integer i [0:4]; wire [15:0] e [0:3] reg [15:0] x [0:3]; initial begin for (i=0; i<4; i=i+1) begin x = MEASURED_AUX6; end end CFBLMS uut (.x_00(x[0]), .x_01(x[1]), .x_02(x[2]), .x_03(x[3]), .e0(e[0]), .e1(e[1]), .e2(e[2]), .e3(e[3])); endmodule Thank you, Shruthi Sampathkumar.