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Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to I
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Hello, As I can see, the basys 3 locked Vivaldo license allows for the use of the ILA (Integrated Logic Analyzer) IP core; artix 7 also shows as a supported fpga family on http://www.xilinx.com/products/intellectual-property/ila.html Looking over Xilinx's ILA documentation (http://www.xilinx.com/support/documentation/ip_documentation/ila/v5_0/pg172-ila.pdf) resource utilization section, it seems the ILA uses quite a bit of logic fabric (though the data is from a Kintex 7 fpga and I don't know how big the resource usage difference is between this family and the artix 7). Have any
